• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 14 subscribers
  • Views 780 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISOW7841: Secondary side power output (VISO) issue

Masanori Tachibana
Genius 5350 points
Part Number: ISOW7841

Hello support team,

I have some questions about ISOW7841.

Our customer is using ISOW7841, and there is a failure that the secondary side power output (VISO) becomes 0 V in several samples.

In the customer's circuit, the decoupling capacitor on the input power supply side is 22 μF.
As a countermeasure, the customer put a bleeder resistor on the secondary output.
Nevertheless, a VISO failure has occurred.

Attach the input power and output power waveforms.

(1) Before measures

(2) After measures

In the above waveform diagrams, P5 is the primary power supply and P5C is the secondary power supply.
Are there any concerns about the cause of the failure of ISOW7841 from these waveform data?
The following points are considered.

1. When power is turned off, the primary power supply is 2.7 V or less (during lockout) and the secondary power supply is not 2.1 V or less
2. When power is turned on, the primary power supply is 2.7 V or less (at lockout), and the secondary power supply is not 2.1 V or less.
3. When power is turned on, power is turned on with a slow slope of 10 ms or more

If you have any measures to prevent ISOW7841 from malfunctioning, please let me know.

Sincerely,
M. Tachibana

  • 0
    TI__Guru 54915 points

    Hi Tachibana-san,

    Sorry to hear about the issue.

    Thank you for providing detailed information related to customer issue. From the power sequencing you have described in points (1) and (2), it looks like VISO didn't turn-OFF completely when VCC turned-OFF. This can lead to unstable output. To avoid this, I would recommend adding one additional 100µF capacitor to ISOW input supply pin VCC.

    For more details on our recommendations, please refer to section 11 in ISOW7841 datasheet titled "Power Supply Recommendations". Please do request customer to follow all the suggestions made in this section of datasheet. This should address the issue that customer is facing.

    Let me know if you have any other questions, thank you.

    Regards,
    Koteshwar Rao

  • 0 in reply to Koteshwar Rao
    Genius 5350 points

    Hello Rao-san,

    Thank you for your reply.

    Our customer and we have already been aware of the datasheet "11. Power Supply Recommendations".
    And the customer and we also understand that it is desirable to put a additional 100 μF of decoupling capacitor to VCC.
    So there are additional questions.

    [Questions]
    1. In the datasheet, the addition of 100 µF is described as “optional”.
    Is the addition of 100 µF to VCC mandatory?

    2. On the customer's board, the decoupling capacitor of VCC is 22 µF.
    There is no space to add 100 µF of capacitor.
    Is it sufficient to replace with 100 µF instead of 22 µF?

    3. The customer added a bleeder resistance equivalent to 10 mA (470 Ω) to discharge the VISO when the power is turned off.
    As a result, the fall time of VISO is faster, and the voltage of VISO drops to 0V when the power is turned off. Despite this countermeasures, defects have occurred. Is it still necessary to add 100 µF?

    4. It takes about 200ms for VCC to rise.
    Does 200 ms of the rise time cause abnormal VISO output or instability?
    “9.3.2 Power-Up and Power-Down Behavior” on page 34 of the datasheet and “11. Power Supply Recommendations” on page 39 state that it is recommended to start up Vcc in 10 ms or less.

    5. If 100 μF of capacitor is added to VCC, the input rise time will be even slower. Should we still add 100μF?
    If so, please tell us why.

    6. Is the relationship of voltage between VCC and VISO critical as a cause of VISO failure?
    If so, please tell us why.

    7. Could you teach us about the background for adding "11. Power Supply Recommendations" from Rev.E to Rev.F in the datasheet?

    The customer needs to urgently take measures.

    Sincerely,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Genius 17100 points

    Hi Tachibana-san,

    These questions will be answered continually as we understand this system.

    The 100uF capacitor is recommended and in this case may be helpful, even with a Vcc rise time >200ms. What causes the fluctuation near UVLO circled in orange below?



    If one capacitor must be selected, please select it so that total capacitance is 100uF greater than the capacitance on Viso. It will be helpful for our team's understanding to view this system's schematics - can you please share these via Personal Message or may I reach out to you via the email on your myTI account? Please do also share the input supply current limit and expected load current conditions at the output.


    Thank you for posting to E2E!

    Manuel Chavez

  • 0 in reply to Manuel Chavez
    Genius 5350 points

    Hello Chavez-san,

    Thank you for your reply.
    I will contact you with a private message.
    I appreciate your continued support.

    Sincerely,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    Genius 5350 points

    Hi Chavez-san,

    I appreciate your great support very much.
    I'll close this thread since you support me separately by E-mail.

    I hope your continued support by e-mail.
    Thank you.

    Sincerely,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Genius 17100 points

    Hi Tachibana-san, all,

    You're welcome! To summarize, our solution so far is to provide a smooth, steady start up for Vcc. While exact implementation has not yet been determined, we are considering the measures from Section 11 of the ISOW7841 datasheet.


    Thank you,
    Manuel Chavez