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ISO721M-EP: Recommended Layout Keep-out

Andrew Frost1
Prodigy 10 points
Part Number: ISO721M-EP
Other Parts Discussed in Thread: ISO721, ISO7721,

Referring to guidance in Developer's Guide: SLLA284B and datasheet SLLS629L, the recommended layer stack figure (figure 9 in SLLA284B) provided implies "no planes, traces pads or vias" should be positioned under the ISO721 on a PCB. Why is this, is this to maintain isolation between the two sides of the isolator, or to reduce EMI? This recommendation does not specify what slew/data rates this is applicable for. Please could you offer some further advice?

Considering the figure only discuses boards of 4 layers, would this still be applicable for a board with many layers? It seems unreasonable to expect all layers should be kept free of features on a many (16) layer design without an explanation of what benefit this constraint provides.

Thanks for your help,

Andy

  • 0
    TI__Genius 17100 points

    Hi Andrew,

    Thank you for posting, and welcome to E2E!

    The recommendation to keep area in a PCB underneath an isolator clear of planes, traces, and vias is to maintain the integrity of the isolation barrier.

    Each side of an isolated PCB should have its own local GND and power supplies; if both sides are connected somewhere in a system, high ground potential differences or transients can easily damage the entire PCB. The purpose of using an isolator is to separate two or more electronic voltage domains, protecting one from potentially damaging electrical conditions the other will be exposed to.

    That being said, although there should not be any electrical connections between both sides of an isolated PCB, a technique to reduce emissions described by Figure 8 of SLLA368C -- an interlayer capacitor, can be implemented by experienced PCB designers so long as the capacitor has enough distance between its layers to maintain sufficient isolation.

    In PCBs with >4 layers, the area beneath an isolator should still be kept completely clear of planes, traces, and vias since high voltages can cause damage from connections on any PCB layer.


    Please let me know if this answer is helpful so far.


    Thank you,
    Manuel Chavez

  • 0 in reply to Manuel Chavez
    TI__Genius 17100 points

    Hi Andrew,

    I'd like to add the additional points to my post above:

    • The width of the isolation barrier and PCB keep-out area is dependent on system requirements. For highest isolation protection, the keep-out region and isolation barrier should be as wide as the isolation device allows it to be. If lower isolation is required, the keep out region can be as thin as 1mm (vs. 4 - 8mm max). Can you share more information on you application's isolation requirements?
    • We recommend using a newer isolation device instead of ISO721M-EP, like ISO7721. ISO7721 is a newer, more robust device with higher isolation ratings. What is the datarate of isolated signals in this system?



    Have a great weekend,
    Manuel Chavez