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Pull up resistor values - Ben hopf please

Hithesh
Genius 3290 points
I was reading TI app note on choosing the correct pull up/down resistor - http://www.ti.com/lit/an/slva485/slva485.pdf
The app note only talks about open collector/open drain ports.
But what about pull ups used in other situations like Reset_n or pulling up the chip select pin of an SPI slave etc (when the ports do not have open drain/collector outputs).
How do you calculate resistor values in those cases. Do you treat the ports as tristate?
  • TI__Expert 7240 points

    Hello Hithesh,

    I think you are asking about how to calculate the value for a pull-up resistor for an ACTIVE-LOW output such as Reset_n or SPI chip select.  Please correct me if I've made an incorrect assumption.

    To calculate the value for a pull-up resistor for these outputs, you can use the method that I used in example 1 of my app note.  The Power Good signal is an active low signal because the IC pulls that pin low when power is not good and lets it float high otherwise.  So for a signal like reset_n, the IC will let that pin float high under "normal" circumstances, but will pull it low when it wants to assert the reset signal.  Just use the same method that I used to find an acceptable value.

    Let me know if my explanation is unclear.

  • in reply to Ben Hopf
    Genius 3290 points

    Ben, thanks for the answer !

    I have one more question - Does the value of pull up limit the max frequency of operation. Let's say a pull up placed on the data line (MISO) line of an SPI bus. 

    If the calculated min/max is 10k and 100k. Would putting 100k limit the max operating freq of the bus?

  • in reply to Hithesh
    TI__Expert 7240 points

    Hithesh,

    That question is outside the scope of my application note as my app note was just discussing digital outputs of DC/DC converters, LDOs, and PMUs.  However, I think I can help you out. 

    In general, the higher the resistor value, the lower the max frequency.  The pull-up resistor creates an RC circuit with the inherit bus capacitance of the line, and a large resistance will cause the RC time constant to be greater, limiting the frequency at which data can be sent.

    This link might prove useful for you:  http://dsscircuits.com/articles/effects-of-varying-i2c-pull-up-resistors.html 

    It gives equations for the max and min pul-up values and provides lab data to show what effect changing the resistor value really has.  It talks about pull-ups for I2C, but the idea is the same for SPI, although the equations will probably be different.

  • in reply to Ben Hopf
    Genius 3290 points

    Ben, I had looked up that link previously.

    If you consider the data line of SPI and I2C, I2C is open collector, where as SPI isn't. 

    Even though you put a high value pull up resistor on SPI data line, wouldn't it be in parallel with internal pull up Mosfet or internal pull up resistor?

  • in reply to Hithesh
    TI__Expert 7240 points

    Hithesh,

    If SPI already has an internal pull-up, why do you want to add an external?

    Also, have you visited this link:  http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=113786?

  • in reply to Ben Hopf
    Genius 3290 points

    Ben Hopf said:

    Hithesh,

    If SPI already has an internal pull-up, why do you want to add an external?

    Also, have you visited this link:  http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=113786?

    Ben, I'm trying to avoid copying a mistake. In one of our boards, we have added pull ups on all SPI lines by mistake. They are following the same mistake in the new boards too. I am trying to justify to my peers that pull ups are not needed on other SPI lines, except CS.

    Thanks for the link.