TPS65381 Question of BIST fail bit and SPI read error (158)

Toshio,

Our applications engineer who is responsible for this device will get back to you in a few days to answer your question. Thank you for your patience.

I' m working on it and will post post the answer once available

Are you referring that SPI error during SAFETY_STAT_3 register read access may not clear status bits because valid SPI read command was not detected. If this is the case, then repeat the same read command again (SAFETY_STAT_3 read command)

Hello Mahmoud-san,

Thank you for your answer.

According to your answer, LBIST_ERR and ABIST_UVOV_ERR are not cleared when SPI read error is occurred.

Please answer additional following question.

Q1:

SFETY_STAT_4 register has SPI_ERR bits. I think BIST error bits are not cleared in case of 01:Command error and 10:Format error, but I have question about 11:Data output mismatch.

Does 11:Data output mismatch detects TPS65381 internal output data and SDO terminal data is different ?

 And Please confirm BIST error bits are not cleared in case of 11:Data output mismatch also.

Q2: How to monitor SPI error.

Device Status Flag Byte Response has following SPI status bit.

STAT[2]: SPI SDO error (during previous SPI frame)

STAT[1]: Data-phase parity (during previous SPI frame)

STAT[0]: Invalid SPI transfer

Please advise if SPI error can be monitored only using these 3 bits or need to monitor SPI_ERR bits of SFETY_STAT_4 register.

Please advise if BIST error bits are not cleared when one of these bit is “1”.

Best Regards.

Hello Mahmoud-san,

Please answer for my post dated Jul 03 2014.

Best Regards.

Hello Mahmoud-san,

Please kindly answer for my question I posted July 03 2014.

Best Regards.

 Q1: SFETY_STAT_4 register has SPI_ERR bits. I think BIST error bits are not cleared in case of 01:Command error and 10:Format error, but I have question    about 11:Data output mismatch. Does 11:Data output mismatch detects TPS65381 internal output data and SDO terminal data is different ?

 [Answer] Yes, data mismatch between internal SDO driver and SDO pin state.

 And Please confirm BIST error bits are not cleared in case of 11:Data output mismatch also.

 [Answer] BIST error bits have nothing to do with Data Output Mismatch (or SDO driver/SDO pin mismatch)

 Q2: How to monitor SPI error. Device Status Flag Byte Response has following SPI status bit.

 STAT[2]: SPI SDO error (during previous SPI frame)

 STAT[1]: Data-phase parity (during previous SPI frame)

  STAT[0]: Invalid SPI transfer

Please advise if SPI error can be monitored only using these 3 bits or need to monitor SPI_ERR bits of SFETY_STAT_4 register.

 [Answer] That is fine. After confirming that one of STAT[x] bits is set and MCU can read additional status registers, but not mandatory. 

Please advise if BIST error bits are not cleared when one of these bit is “1”.

[Answer] BIST error has nothing to do with SPI Status bits that are communicated with each SPI response to received SPI command.

Hello Mahmoud-san,

Thank you for your answer.

I’m sorry, some questions were not appropriate.

So could you please answer following questions again?

1)     Please confirm that BIST error bits are not cleared when 11:Data output mismatch SPI error occurred.

2)     Please confirm that BIST error bits are not cleared when one of following Device Status Flag Byte bit is “1”( SPI error occurred).

         STAT[2]: SPI SDO error (during previous SPI frame)

         STAT[1]: Data-phase parity (during previous SPI frame)

         STAT[0]: Invalid SPI transfer

Best Regards.

Hello Mahmoud-san,

Please answer for my additional question.

Besr Regards.

Hello Mahmoud-san,

Please answer for my question.

Besr Regards.

Hello Mahmoud-san,

Please answer for my question.

Besr Regards.