Dear Experts,
I using Blackhawk USB560v2 to debug TDA2x.
They encountered an error when perform the "Test Connenction" in CCS v6.
The JTAG test log is copied as below.
Does anyone know what is wrong with the connection?
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[Start: Blackhawk XDS560v2-USB System Trace Emulator_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\ryuhs74\AppData\Local\TEXASI~1\
CCS\ti\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
The library build date was 'Feb 19 2015'.
The library build time was '00:08:17'.
The library package version is '5.1.641.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv6\ccs_base\common\uscif\dtc_top.jbc
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 512 - 01 00 500.0kHz O good value measure path length
2 512 + 05 20 48.00MHz [O] good value apply explicit tclk
The first internal/external clock test was not done.
The second internal/external clock test was not done.
In the scan-path tests:
The test length was 16384 bits.
The JTAG IR length was 6 bits.
The JTAG DR length was 1 bits.
The IR/DR scan-path tests used 2 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 48.00MHz as the highest frequency.
The IR/DR scan-path tests used 48.00MHz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.
The value is '-286' (0xfffffee2).
The title is 'SC_ERR_CLK_PLL_HUNG'.
The explanation is:
The PLL programming function has suffered a timeout.
This may be an honest-to-goodness software or VHDL bug.
[End: Blackhawk XDS560v2-USB System Trace Emulator_0]
