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DRV3201 Issue

umamaheswar peta
Expert 1370 points

Hi,

we are facing some issues in DRV3201 for driving a BLDC motor.

 We have used the component design as per the application note SLVU846A–January 2013–Revised July 2013. 

Please find the attached screenshots of output pins of the DRV3201 and the Schematics FYR.

Similar waveforms observed in all the 3 HighSide and 3 Lowside pins.

  • No error on the ERR pin.
  • As you see, Higgside PWMs are shifted from zero and we cannot understand the reason.
  • Our settings,

 

  • a)
  • 1 EN
  • 0 DRV_OFF
  • 1 B_EN
  • 1 RSTN
  • 1 CSM
  •  
  • b)
  • 1: Unlimited HS/LS currents for rising/falling edges
  • 0: Set PWM mode
  • 1: ERR pin configuration
  • 0: Enable LS VDS error handling in CSM
  • 0: Enable HS VDS error handling in CSM
  • 0: Enable programmable dead time in CSM
  • 0: Enable boost under voltage handling in CSM
  • 0: Enable VS overvoltage handling in CSM

Embitel.docx

  • 0
    TI__Expert 3555 points

    Hi Umamaheswar,

    Are the waveforms provided measuring the gate pin with respect to ground? (GHSx & GLSx pins)

    The output of the gate pins will always be with respect to the source pin of the same gate (SHSx & SLSx pins). The voltage from the gate to source will be between 9V and 12.8V if the design is working correctly (this is from the DRV3201 spec on page 6). On your board the low side source is connected to ground through the sense resistor, so the waveform will be from ground as the second image shows. In the case of the high side, the source is floating. When the high side source is floating it will float up to near the VS voltage.

    Unfortunately I cannot fully read the the labels from the waveform image in the word document. Can you attach a picture that is more clear?

    Can you also provide the following:

    • Voltage on the VS Pin
    • Measured Voltage on the BOOST pin

    Regards,

    Will Toth