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UCC28950-Q1 - some questions

Hirotaka Matsumoto
Guru 27585 points
Other Parts Discussed in Thread: UCC28950-Q1

Hi all

Would you mind if we ask UCC28950-Q1?

<Question1>
About Master and Slave mode formula from (15) to (19) on the datasheet, our customer uses one circuit.(there is no slave)
In this case, they had better use (15), (17) and (19), right?
When they would like to use slave mode, is the setting as follows?
-The setting-
To set the converter in slave mode, connect the external resistor RT between the RT pin and GND, and place an 825-kΩ resistor from the SS pin to GND in parallel to the SS_EN capacitor. This configures the controller as a slave.

<Question2>
On the formula (15), there is "Ids(master)=(-25×(1-D)+5)uA".
Duty is maximum 97%.
In case of D > 0.8,  the value of Ids(master) will be plus value.
Does it mean that CSS is not discharged? Otherwise,  is it charged?
If it is charged, the voltage of SS pin does not decrease, does the switching keep on?

We need your help.

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Genius 16410 points
    Hello Matsumoto-san,

    <Question1>
    Yes you are correct, use 15/17/19 for the master converter. And your statement about setting slave mode is correct, as described in the "Switching Frequency Setting" section of the datasheet. You can also connect the SYNC pins together, and the slave will synchronize to the master's clock with 90 degree offset.

    <Question2>
    The "D" in the formula should be the duty cycle including the current limiting function. Since the output is disabled once CS reaches 2V, this will limit the duty cycle based on the waveform of CS. This should limit the duty cycle lower than 80%, which will cause SS to discharge and reset the converter. If D > .8, the CSS won't increase, but will likely stay at 4.65V from cycle-to-cycle and switching would continue, though this would only happen if CS is below 2V for 80% of the switching cycle.

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    Guru 27585 points

    Karl san

    We have some additional questions from our customer.

    <Question1>
    If the Duty is limited, we guess that the out put voltage will be below(down).
    When the current clope for CS pin increases, the duty will be below, furthermore the out put voltage will be much below.
    With repeating this operation, finally the Duty will be 0, and out put voltage will be 0.
    So, in this process, SS pin voltage is typ3.6, at the time, will the Duty 0?

    <Question2>
    TCL is decided by IDS, right?
    When CS=2V, TCL is changed by D, and relation to <Question1>, according as the Duty is below, TCL will be below.
    Is this recognition correct?

    <Question3>
    On the datasheet, it shows TCL=5ms in case of CSS=0.1uF.
    However, this condition is D=0, so is TCL=5ms actual minimum value?

    We appreciate your help always.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Genius 16410 points
    Hi Matsumoto-san,

    <Question1>
    > If the Duty is limited, we guess that the out put voltage will be below(down).
    Yes, I agree.

    > When the current clope for CS pin increases, the duty will be below, furthermore the out put voltage will be much below.
    > With repeating this operation, finally the Duty will be 0, and out put voltage will be 0.
    > So, in this process, SS pin voltage is typ3.6, at the time, will the Duty 0?
    This should depend on how much current the load is trying to pull. If there is a very hard short, the duty will be 0, or very close to 0. This duty cycle should depend on TCLon time, compared to how much the CS voltage increases. If CS stays close to 2V (eg. soft over-current condition), the duty cycle may not go to 0.

    <Question2>
    > TCL is decided by IDS, right?
    TCLon is decided by IDS. TCLoff uses a fixed 2.5uA current source. I think you're talking about TCLon in this question.

    > When CS=2V, TCL is changed by D, and relation to <Question1>, according as the Duty is below, TCL will be below.
    > Is this recognition correct?
    Yes, if the duty cycle decreases, the IDS current will increase, and therefore the TCL time will be lower.

    <Question3>
    > On the datasheet, it shows TCL=5ms in case of CSS=0.1uF.
    > However, this condition is D=0, so is TCL=5ms actual minimum value?
    5ms is the minimum TCLon time for 0.1uF capacitor. If D>0, the IDS current will decrease, and therefore the TCLon time will be longer. However you can have a shorter TCLon condition by using a lower Css, but this also changes the soft start time.

    Regards,
    Karl