TPS3820-33QDBVRQ1

 1. The connected microprocessor can drive the nRST
   pin low, provided that it can sink >400uA
   (datasheet, p7, Ios & Note 4).
1a.   No series resistor is required for nRST ?

A resistor is not required.

1b.   On being driven low (nRST), the TPS3820 will limit Ios
      to <400uA; there will not be a transient current
      spike greater than this?

The 400uA spec is the maximum current that the internal high-side switch can supply. There should not be a transient current spike unless it comes from an external source.

1c.   A low pulse on the device's nRST line does not
      initiate a new reset cycle?

A low pulse on the RESET output should not initiate a reset cycle, but a pulse on the RESET input will.

2. Momentary glitches (<tw = 6us) on Vdd below Vit-|max = 3V
   will not trigger a reset. 

   I believe figure 8 is a TYPICAL plot. For what temperature
   is it valid?

A low pulse on the RESET output should not initiate a reset cycle, but a pulse on the RESET input will.

3. nRST delay time is specified as 15 <= td <= 37ms at
   25degC. 

   What is the MAX spread of this parameter over the
   -40...+125degC device operating range?

Characterization was not performed on this device. It was released by similarity to the TPS3823. The TPS3823 characterization data shows that the delay time may exceed the 25C value below 0C.

4. Watchdog timeout is specified as 112ms <= ttout <= 310ms
   at 25degC.
  
   What is the MAX spread of this parameter over the
   -40...+125degC device operating range?  

The TPS3823 characterization data shows that the watchdog timeout meets the datasheet value over temperature.  

 Tom,

thanks for your support and answering the questions in no time.

I have still a question regarding question 2.  Does a glitch, smaller then 6us, on pin VDD of the WD (not the reset pin) trigger a reset of the WD ? Figure 8 in the datasheet seems to show this behaviour, but at which temp. is this plot valid ?

Regards,

Matthias

I did not collect the data for the graph om Figure 8, but my interpretation is that the minimum pulse width required is dependent on how far VDD drops below Vit-. In the case of Vit- +/- 200mV, as presented in the timing requirements, the pulse width for VDD = Vit- -200mV is about 3us and the pulse width for VDD = Vit- + 200mV is about 3us for a combined total of 6us. If VDD drops lower and / or transitions higher, then the required pulse width of the glitch my be smaller. A valid Vdd pulse width will reset the WD monitor.  

I think that  WDI and MR/ were left open in this data to make sure that they were deactivated and did not affect the test.