Linux/TMS320DM8148: SPI controller can't read register with variant size ?

Hi Ran,

From what I understand you have issue when trying to read data from a register? DM814x SPI read this data from external device? What do you mean by "9-bit address"?

DM814x SPI module has wide selection of SPI word lengths ranging from 4 bits to 32 bits. SPI configuration is per channel (clock definition, enable polarity and word width). SPI supports any SPI word from 4 to 32 bits long. The SPI word length can be changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.

Regards,
Pavel

Hi Pavel,

Please take a look at the following example.

• CS need to be down for both control&data.
• control length is 9 buts.
• data length is 8 bits.

If I use spi_write_then_read, it will change CS for both tx and then for rx, Right ?

I need somehow to force CS active for both tx&rx .

How can I use different word length for reading this 8-bit register ?

Can I also force CS inactive during tx&rx (control write & data read ) ?

Best Regards,

Ran

Ran,

Ran Shalit said:

• control length is 9 buts.
• data length is 8 bits.

Ran Shalit said:

How can I use different word length for reading this 8-bit register ?

Do you mean that you need to write/send 9-bit command, then read/receive 8-bit data? Do you use DM814x SPI as master? The spi_write_then_read() function allow to set the size in bytes, 1 byte (8-bit), 2 bytes (16-bit), etc. I think the problem is in the 9-bit command, is that correct? Or you mean something else? What exactly you mean by "different word length for reading 8-bit register"?

Ran Shalit said:

If I use spi_write_then_read, it will change CS for both tx and then for rx, Right ?

Ran Shalit said:

I need somehow to force CS active for both tx&rx .

Ran Shalit said:

Can I also force CS inactive during tx&rx (control write & data read ) ?

In master mode, the SPI_SCS[n] line must be negated and reasserted between each successive SPI word. This is because the slave select pin freezes the data in its shift register and does not allow it to be altered if PHA bit equals 0.

The assertion of the SPI_SCS[n] signals is programmable: SPI_SCS[n] signals can be manually asserted or can be automatically asserted.

SPI_SCS[n] kept active between words, programmable with the bit MCSPI_CHxCONF[20] FORCE

For more details see section 22.2.3.6.2 Keep SPI_SCS[n] Active Mode (Force SPI_SCS[n])

Regards,
Pavel

Hi Pavel,

"Do you mean that you need to write/send 9-bit command, then read/receive 8-bit data? "

Yes.

"In master mode, the SPI_SCS[n] line must be negated and reasserted between each successive SPI word."

I must deactivate CS during command and data , so I mustn't allow " SPI_SCS[n] line must be negated and reasserted between each successive SPI word." . Is that possible to achieve using cs force ?

Is there any linux API for this purpose, or should I achieve it by directly writing into registers ?

Regards,

Ran

Ran Shalit said:

I must deactivate CS during command and data , so I mustn't allow " SPI_SCS[n] line must be negated and reasserted between each successive SPI word." . Is that possible to achieve using cs force ?

Yes, I think it is possible. Using the force bit, the CS line will stay active/asserted until you write again in force bit.

Ran Shalit said:

Is there any linux API for this purpose, or should I achieve it by directly writing into registers ?

linux-2.6.37/drivers/spi/omap2_mcspi.c

omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)

You can also check how this function evolve in the latest TI PSDK which comes with linux-4.4.32

linux-4.4.32/drivers/spi/spi-omap2-mcspi.c

omap2_mcspi_set_cs(struct spi_device *spi, bool enable)

Ran Shalit said:

"Do you mean that you need to write/send 9-bit command, then read/receive 8-bit data? "

Yes.

So the problem is that spi_write_then_read() set the size in bytes (1 byte, 2 bytes), while you need to set 9 bits, is that correct? Or you have other issue here?

Regards,
Pavel

Hi Pavel,

So the problem is that spi_write_then_read() set the size in bytes (1 byte, 2 bytes), while you need to set 9 bits, is that correct?

I think spi_write_then_read doesn't set the size, but only spi->bits_per_word, set word size.

The problem is :

1. forcing cs active for both control&data , and only then deactivate it.

2. control word is 9 bits and data word is 8 bits.

I tried to achieve it, but had no success so far. If there is some example it may help.

I tried as following:

 spi->mode |= SPI_NO_CS;
spi->bits_per_word = 9;
spi_setup(spi);
 omap2_mcspi_force_cs(spi, 1);

status = spi_write_then_read(spi, (const u8 *)&addr_reg, 2,(u8 *) data, 0);
spi->bits_per_word = 8;
spi_setup(spi);

status = spi_write_then_read(spi, (const u8 *)&addr_reg, 0,(u8 *) data, 2);
 omap2_mcspi_force_cs(spi, 0);

I am not sure that SPI_NO_CS is supported in mcspi.

Regards,

Ran