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DAC5675-EP Clk Driver

Kim Xin
Prodigy 50 points
Other Parts Discussed in Thread: DAC5675-EP, DAC5675

Hi,

I was wondering how I can drive the clocks of DAC5675-EP with LVDS. I am using LVDS outputs of an FPGA to generate clocks for the DAC, however, the DAC accepts LVPECL. 

After looking at the data sheet, I did not find a schematic suggesting how I can convert/connect LVDS to LVPECL to be used as the clock input. By the way, on page 15 of the datasheet, Fig 16, it shows an internal biasing for the clocks, so I am a bit confused why in Fig. 18 another external biasing circuit was used.

Thanks for your help

  • 0
    TI__Mastermind 20541 points
    Hi Kim,

    I moved your question to High Rel. group forum.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    TI__Expert 4420 points
    Kim, the apps engineer that supports this device is out today. He will back at the office tomorrow and will address your questions then. Thanks,
    JV
  • 0 in reply to Javier Valle
    Prodigy 50 points
    Hi Javier,
    Thanks for your reply. I was wondering if the apps engineer got a chance to look at the datasheet to help me solving the problem.

    Thanks,
    Kim
  • 0
    TI__Guru 62930 points
    Kim,
    I think your best bet is to use the following reference for LVDS to LVPECL AC coupling.
    www.ti.com/lit/an/scaa059c/scaa059c.pdf
    Figure 10 shows this. However, in this case the termination should be moved to the other side of the AC coupling caps (as in figure 18) since the DAC5675 will set internal biasing. (no VBB pin) These should be close to device.

    The reason in Fig 18 that there is external biasing, is that it is providing termination to the source driver prior to the AC coupling. The DAC5675 will internally set common mode and biasing.

    Just a note, using an FPGA generated clocks may not have best AC performance due to jitter.
    Regards,
    Wade