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How do I demonstrate the gain and phase margin of a DCDC and/or LDO

Kévin Stoffels
Prodigy 70 points
Other Parts Discussed in Thread: TPS7H1101-SP, TPS50601-SP

Hello everybody, could someone help me with this question :

How do I demonstrate the gain and phase margin of a DCDC and/or LDO ?

In one of my project, I am using a TPS50601-SP DCDC and a TPS7H1101-SP LDO, I used webench to make my designs and one of my customer ask me to answer this question :

The control loops of TPS50601-SP and TPS7H1101-SP POLs implementation appears not to have been verified, and the schematics does not include any preparations for this measurements, 10dB gain margin and 50 dB phase margin must be demonstrated (ECSS).

How can I do that ? Could you help me finding some reference document or give me the way to proceed ?

Best Regards,

Stoffels Kévin

  • 0
    TI__Expert 7445 points
    Kevin,

    For TPS50601-SP you can measure the gain/ phase by running a bode plot. Use tool like Venable analyzer or Ridley analyzer as AP300 and you should be able to plot gain/ phase .
    With regards to TPS7H1101-sp as it has multiple loops one can not run conventional bode plots. However you can demonstrate stability by doing transient ( step-load) response. or Alternately measure output impedance using Bode 100 from picotest and by measuring group delay - thus converting it to phase margin. See Stability section in TPS7H1101-SP datasheet pg. 14 for more details.