Other Parts Discussed in Thread: ADC128S102
Hello,
We are working with the ADC128S102QML-SP in our application, we connected 3.3V to both VA and VD. We are using an FPGA with the IO voltages operating at 3.3V to drive the SCLK, CS & DIN; and we are not performing an ADC conversion at power up (there’s at least 100 ms of power on reset before the FPGA starts to process any data). That being said, should there be a concern with our application based on the highlighted item below?
Below is a copy of section 8.2.1 and the highlighted section is my concern. I have two additional questions:
- Why does VA have to be separated from VD when the MCU is operated by 3.3V or lower?
- Why does VA has to be powered up before VD?
8.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing up to eight single-ended input signals ranging
from 0 to 5 V with BW = 10 kHz and a throughput up to 500 kSPS. The ADC128S102 has to interface to an MCU
whose supply is set at 5 V. If it is necessary to interface with an MCU that operates at 3.3 V or lower, VA and VD
will need to be separated and care must be taken to ensure that VA is powered before VD.
There are couple of more items in the data sheet that contradict the highlighted section 8.2.1 above. First, the last sentence in section 9.1 states: “VA must ramp before or concurrently with VD” to avoid turning on the ESD diodes. This indicates that VA and VD can be powered up at the same time. Second, all the test conditions for the Electrical Characteristics in sections 6.5 thru 6.7 show VA=VD=3V or 2.7V. This indicates that VA and VD can be tied together at 3.3V or lower.
Thank you for helping to clear my confusion.
