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TLV2548-EP: TLV2548-EP timing delay between last SCLK and rising CS question.

Ashley Scott
Prodigy 210 points
Part Number: TLV2548-EP


How do I Set the timing for the CS signal WRT SCLK? The recommended operating conditions suggests that the delay from the 16th falling edge of SCLK to the rising edge of CS should be a minimum of 0.5 SCLKs, which means (I think) that I should wait until after the rising edge of SCLK before I bring CS high, but the description of CS on page 2 suggests that CS should go high while CLK is low. Can someone help me clear up this confusion?

  • 0
    TI__Guru 62930 points
    Ashley,
    I apologize for the delay. I was out of the office, and this was missed by those covering for me.
    The specification for this older device is not as ideal as it could be.
    With that said, I believe it is indicating that at least 1/2 a cycle needs to be delayed after 16th rising edge.
    What I am not sure about is implications of the note on page 2 indicating that CS should transition only during rising SCLK.
    I will follow up with experts and confirm this. It sounds like it may violate standard SPI protocol if happens during falling edge though will still work.
    Also, this other post may be of help to you.
    e2e.ti.com/.../558500

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    TI__Genius 16890 points

    Hi Ashley,

    The Recommended Operating Conditions should be followed, which says that after the falling falling edge of the 16th clock you should wait at least 0.5 clock cycle before bringing CS high.  After the the 16th clock falling edge just keep the SCLK signal low and then bring CS high after a wait of 0.5 clock cycle.

    The CS note on page 2 is shown in Figure  20.  The The 16th SCLK pulse has a rising and falling edge and then stays low.  Then CS is brought high.  CS according to the note should not be brought high while SCLK is high.  So, if you had a 17th or more clocks you should wait until the clock is low before bringing CS high.

    Mike