Other Parts Discussed in Thread: DAC121S101QML-SP,
We will be using both the ADC128S102QML-SP and the DAC121S101QML-SP in a LEO satellite.
Due to SEUs on the SCLK line there may be short spikes, which will violate the maximum clock frequency spec.
How will the ADC and the DAC react in such a situation?
Will the current transaction just lead to an invalid result or may the circuits actually "hang up" in some form or other?
Regards,
Klaus