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OMAPL138B-EP: EMIFA communicates with asynchronous devices

Aobo Guan
Prodigy 110 points
Part Number: OMAPL138B-EP


Hello,

I got a question on communicating with asynchronous devices through EMIFA and taking https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/586792/2155382 as reference. 

My questions are:

1. Which register(s) should I configure? PSC, PINMUX, CE5CFG (I'm using CS[5] as chip select to the device). Any other register?

2. What's the address of pin EMA_D, EMA_A, EMA_BA? In other words, if I want to R/W information from/to the device through these pins, which address should I access? The StarterWare nand flash R/W example defines a couple of addresses as shown in figure below, but I cannot understand the 0x08 and 0x10 offset.

nandInfo->dataRegAddr = (SOC_EMIFA_CS3_ADDR + 0x00);
nandInfo->addrRegAddr = (SOC_EMIFA_CS3_ADDR + 0x08);
nandInfo->cmdRegAddr = (SOC_EMIFA_CS3_ADDR + 0x10);

Is the "dataRegAddr" mapped to EMA_A? "addrRegAddr" mapped to EMA_A and EMA_BA?

3. How can I control the chip selection (CS[x])? Modify specific register?

Regards,

Albert

  • 0
    TI__Mastermind 27355 points

    Hi Albert,

    If you have not done so already, I recommend reading through the EMIFA chapter of the TRM. Specifically, sections 20.2.5.1 and 20.2.5.3.

    Figure 20-9 shows the mapping of the address lines between the EMIFA and device.The offsets you mentioned are explained in section 20.2.5.6.3 Driving CLE and ALE.

    I hope this helps. Please let us know if you have any questions.

    Regards,

    Sahin

  • 0 in reply to Sahin Okur
    Prodigy 110 points

    Hi Sahin,

    Thanks for your response, but I'm still confused with the mechanism of EMA_A. I set the ASIZE of CE3CFG to 1 to select a 16-bit bus. And if I understand Figure 20-8 b) of chapter 20.2.5.1 correctly, the EMA_BA[1] is the least significant bit of the address, and EMA_A[x:0] should be other bits. So I test it with code below:

    *(volatile unsigned short*)(0x62000008u) = 0x0000;
    *(volatile unsigned short*)(0x62000008u) = 0x0002;
    *(volatile unsigned short*)(0x62000008u) = 0x0004;
    *(volatile unsigned short*)(0x62000008u) = 0x0008;
    *(volatile unsigned short*)(0x62000008u) = 0x0010;

    0x62000008 is the address of Address Register according to StarterWare example.

    And I monitor the EMA_A[4:0] which suppose to be bit 5:1 of the address. And I also monitor the EMA_WEn signal.

    Since we have written 0x0 to 0x10, I expected A[5:0] should be read as 0x0 to 0x08. But the level of those lines are only changed at the first falling edge of the EMA_WEn signal.

    Thanks,

    Albert

  • 0 in reply to Sahin Okur
    Prodigy 110 points

    Hi Sahin,

    Aha, your guidance on 20.2.5.6.3 helps me a lot! I think it makes sense now:

    Here is another test:

    *(volatile unsigned short*)(0x62000008u) = 0x0000;

    *(volatile unsigned short*)(0x62000010u) = 0x0002;

    *(volatile unsigned short*)(0x62000008u) = 0x0004;

    *(volatile unsigned short*)(0x62000008u) = 0x0008;

    *(volatile unsigned short*)(0x62000008u) = 0x0010;

    And those addresses are changed:

    Those address line expresses the address offset where we R/W data which is even more convenient than I thought!

    Thanks a lot!

    Appreciate,

    Albert