• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 13 subscribers
  • Views 1038 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1282-SP: timing, Tdr

Mike Valvo
Intellectual 470 points

Part Number: ADS1282-SP

(assuming Chris Hall is answering)

hi Chris, I'm having some trouble understanding the timing when in pulse-sync mode, specifically Tdr. 

assuming that Fclk=3.125MHz and Sclk=1.5625MHz:

once I assert the SYNC pin, DRDY goes high and then it will go low again after a period of Tdr.  According to section 7.7, Tdr depends on which filter you're using, the sample rate, and the clock rate.  

so if I'm only using the SINC filter with the default data rate of 32kSPS, then Tdr=968/3.125E6 = 310us. is that correct?

if I'm using the SINC + FIR filter with the default data rate of 1000SPS, then Tdr= 63/1000 + 466/3.125E6 = 63ms.  is that correct?  Section 7.7 gives Tdr for Sinc and FIR individually.  should I add them together if in SINC+FIR mode?

Assuming SINC filter only, the SYNC pin is asserted, then Tdr time passes and DRDY goes low, then I take 32 Sclks to send the RDATA command, and then according to section 7.9, it will take another 1/Fdata for Tdr to go low again, then I take another 32 Sclks to read the data in.  so the total time would be ~(1.28us + 310us + 20.48us + 31.25us + 20.48us) = 383.49us (SYNC + Tdr + RDATA + Tdr + DATA)

is that correct?

(all of the numbers in the datasheet seem to assume that Fclk=4.096MHz.  what if it's not?)

  • 0
    TI__Genius 14540 points

    Hi,

    All parametric specifications and typical plots were measured using fCLK=4.096MHz.  However, I believe all timing specifications are written as a function of fCLK and fDATA rates, so these need to be calculated based on an application, as you have done.

    so if I'm only using the SINC filter with the default data rate of 32kSPS, then Tdr=968/3.125E6 = 310us. is that correct?

    [CY]  Correct

    if I'm using the SINC + FIR filter with the default data rate of 1000SPS, then Tdr= 63/1000 + 466/3.125E6 = 63ms.  is that correct?

    [CY] The 1000SPS data rate is obtained with fCLK=4.096MHz.  Since you have reduced fCLK to 3.125MHz, the data rate will also reduce and the realized data rate will be 763SPS.  Therefore, Tdr=63/763 + 466/3.125e6 = 82.7ms.  

    Section 7.7 gives Tdr for Sinc and FIR individually.  should I add them together if in SINC+FIR mode?

    [CY]  The FIR filter has fixed decimation while the SINC filter has programmable decimation.  The Tdr of the SINC filter is dependent on this decimation state as shown in Table 21.  Therefore, the Tdr of the FIR filter should be added with the Tdr of the SINC filter.

    Assuming SINC filter only, the SYNC pin is asserted, then Tdr time passes and DRDY goes low, then I take 32 Sclks to send the RDATA command, and then according to section 7.9, it will take another 1/Fdata for Tdr to go low again, then I take another 32 Sclks to read the data in.  so the total time would be ~(1.28us + 310us + 20.48us + 31.25us + 20.48us) = 383.49us (SYNC + Tdr + RDATA + Tdr + DATA).  is that correct?

    [CY] A few corrections:  According to section 7.9, it will take between 0/Fdata and 1/Fdata for Tdr to go low again, or 0-31.25us.  Figure 55 from the datasheet shows the timing when using RDATA command.  This command is only 8bits, not 32bits as in your calculation.  Also, read continuous data mode must be cancelled by sending the SDATAC command before invoking RDATA command.  Also, as shown in Figure 57 there is a 24/fCLK minimum delay required between command writes.   

    Regards,

    Christian

  • 0 in reply to Christian Yots
    Intellectual 470 points

    thanks Christian, that helps a lot. 

    one quick question: if I'm never operating the chip in read continuous mode, do I still have to send the SDATAC command before the RDATA command?

  • 0 in reply to Mike Valvo
    TI__Genius 14540 points
    Hi again,

    The default state of the device is Read continuous mode but once you deactivate this mode with SDATAC command, this read continuous mode remains disabled until a powerdown or reset is initialized on the devcie. You must only send the read data command before each data conversion.

    8.3.23.2 Read Data by Command
    The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read
    by command. In the Read Data By Command mode, a read data command must be sent to the device for each
    data conversion (as shown in Figure 55). When the read data command is received (on the eighth SCLK rising
    edge), data are available to read only when DRDY goes low (tDR). When DRDY goes low, conversion data
    appear on DOUT. The data may be read on the rising edge of SCLK.

    Thanks,
    Christian