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SM470R1B1M-HT: Power on reset

JIN CAI
Prodigy 20 points
Part Number: SM470R1B1M-HT

Hi Wade,

I am using SM470R1B1M-HT and have an issue with power on reset of the microcontroller, hopefully can get supports from you.

 

To have a reliable power on reset, a voltage supervisor (TI TLV803S with 2.93V threshold and 200ms delay) is used to monitor VCCIO which is from a 3.3V DC power supply with a current limit setting of 500mA. VCC (1.8V) is generated by a LDO regulator from the VCCIO and the VCC comes with 5ms delay compared to the VCCIO.

 

The RESET output of the voltage supervisor is connected to PORRST pin with a 10k pull-up resistor. During the power on reset test, I found that sometimes the microcontroller cannot have a good reset and sank high current from the DC power supply.

I also did another test that the PORRST was connected to GND during power on and then released. I still found that sometimes the microcontroller didn’t stay in reset status when PORRST was held to GND and sank high current from the DC power supply.

Do you have any comments on this case?

Thanks,

Jin

  • 0
    TI__Guru 62930 points

    Jin,
    Can you provide scope plots of the VCCIO, VCC, and PORRST during power up?

    On your other comment with respect to sinking high current when PORRST is held low. Are you indicating current was high, even when held in reset with PORRST?

    Do you know what supply is sinking the current? VCC or VCCIO?   How much current?

    Can you provide a schematic of R1B1M for review?

    Has this occurred on more than one board?

    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 20 points

    Hi Wade,

    Thank you for your quick response.

    Please see below scope plots for the VCCIO, VCC, and PORRST during power up. The first one is for VCCIO (CH1) and VCC (CH2) , the second one is for VCCIO (CH1) and PORRST (CH2).

    For the test when PORRST is held low - there are two results in different test condition. If the 3.3V power is ready first, then connect VCCIO to the 3.3V, most likely the MCU can stay in reset state with very low current (few mAs) from the 3.3V. But if the 3.3V is not ready (the power supply is off) and VCCIO is connected to the 3.3V terminal, then power on the power supply, the MCU could not stay in reset state and sink high current from the 3.3V source. The test result is the same when PORRST is controlled by the voltage supervisor and VCCIO is powered in the two different ways. It seems that the different rising rate of VCCIO results in a different result.

    Currently I could not check if the high current comes from VCCIO or VCC because I need to use two individual 3.3V power sources and change connection on the board.

    This behavior occurred on more than one board. I can send your the SCH for review. Could you please give me your email?

    More Information: I think the high current is from VCCIO. When reset failed, the VCCIO is just around 2V and VCC out is 0V.  The 3.3V output for VCCIO could not keep at 3.3V because the 3.3V power supply has a current limit setting of 600mA.

    Thanks,

    Jin

  • 0 in reply to JIN CAI
    TI__Guru 62930 points
    On the surface, the timing appears to meet spec for power up.
    I sent email to you so you can provide schematic.
    Regards,
    Wade