Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 18 subscribers
  • Views 223 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LS161A: CLK Input Signal Rise-Time Question

Darren (FAE)
Expert 5483 points
Part Number: SN74LS161A

1) Is V_IH and V_IL from the EC Table in the Datasheet also valid for the CLK Input?
i.e. would the CLK need a voltage higher than 2V(min) to register a rising edge?

2) What is the required rise/fall time of the CLK signal, to make sure a slow transition from Low -> High doesn't cause some kind of glitch?
Would a 1[ns] rise-time though the transition region cause any issues?

3) Assuming the following:
Fclk = 8MHz
LOW = 0V
HIGH = 5V
Duty = 50%

Do you see any issues with a 1[ns] rise-time through the transition region?

Regards,
Darren

  • 0
    Guru 279060 points

    1. The specifications apply to all inputs, including CLK.

    2. The required minimum input rise/fall rate is specified in the datasheet in table 1 of some application note; it's 15 ns/V.

    3. 1 ns is extremely fast; the maximum would be (2 V − 0.8 V) × 15 ns/V = 18 ns.

  • 0 in reply to Clemens Ladisch
    TI__Expert 5483 points

    Hi Clemens,

    That is really helpful!

    Let me follow-up with a clarification, sorry.
    The actual rise-time is a little longer (confirming if it meets >15ns/V), but the application I am supporting sees CLK having a "flat plateau" around 1.5V during the rising edge, that lasts for about 1ns.

    From the above comment, would a ~1ns plateauing around the "undefined" regions between 0.8V ~ 2V cause any output "Q" H/L latching issues...etc?
    Or, I guess what I am asking is during the rising edge, how long could you "remain" in the undefined range (0.8V ~ 2V) before causing trouble?

    Is there any material that discusses this...?

    Regards,
    Darren

  • 0 in reply to Darren (FAE)
    Guru 279060 points

    A flat plateau is slower than 15 ns/V. But it cannot cause latching; the worst that could happen would be oscillations at the output, but for 1 ns, that's unlikely.