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SN74LVCH16T245: When the power is turned on、the signal behaves strangely

Yoichi Tanaka
Prodigy 10 points
Part Number: SN74LVCH16T245
Other Parts Discussed in Thread: SN74AHCT16541
We are using SN74LVCH16T245.

A side connect the power supply +3.3V ,and connect the FPGA output (LVCMOS3.3V). 
B side connect the power supply +5V ,and connect the input of ULN2803ADWR.
The direction is A → B. 
All OEs are GND. ALL DIR is +3.3V connection.

The attached photo shows the waveform on the B side (8 pin) of the SN74LVCH16T245 on the top, and the rising waveform of the +3.3V power supply on the bottom.
It is unclear that the waveform on the output is in the signal of about 2V, probably because the direction changes from B to A until +3.3V rises.
In addition, +5V has started up firster than +3.3V. 
Probabily,FPGA signal is in the OPEN state.


Please tell me the reason for this phenomenon.
And please tell me the cause and countermeasures.

 
  • 0
    Prodigy 10 points 
    I will attach a waveform photo。

  • 0
    Guru 316440 points

    The minimum supply voltage at which correct operation is guaranteed is 1.65 V.

    The datasheet says:

    To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor.

    And there is no guarantee that floating bus-hold inputs power up in the desired state.

    I see two alternatives:

    1. Enable OE only after the FPGA has powered up and outputs valid signals; or
    2. use a buffer with TTL-compatible inputs (e.g., SN74AHCT16541) as level shifter, and add pull-down resistors at its inputs; it runs only from the 5 V supply, so its outputs will drive low before the 3.3 V supply powers up.