Other Parts Discussed in Thread: LSF0108
Hi,
I have a cascaded buffering scheme for SPI chip select which flows as shown below,
Micro Controller --> 1x SN74LVC125A --> 8 x 74HC154 (Demux) -->1x LSF0108 --> Destination.
Consider the trace length from SN74LVC1524 will be 20cm per each the load(74HC154).
Will there be any translation issues between this scheme.