LSF0108: Voltage on low side too high

Bert Thomas

Part Number: LSF0108

Hi, I am working on a design with a 5V microcontroller that needs to interface to a 3.3V memory. For this I added a bunch of LSF0108s. For testing purposes I have nothing connected to the low end (A), with the microcontroller I can use GPIO to set each B-side input. When the GPIO is low, the A-side is low too, so far so good. But when the GPIO becomes high (5V) the A-side becomes around 4V. Again, this is with no load connected. The memory chip I'm using specifies its input current as 1uA maximum, so no pull-ups should be necessary I guess. To simulate that load I added a 1.5M resistor from the A-side connection to ground. Then the voltage drops to 3.5 to up to 3.8V. I am afraid to solder the memory chip on the PCB as the higher voltages might damage the device. So why is the voltage on the A-side so high and not clamped to it's 3.3V ref?

This is the schematic: The memory IC is CY14B104

over 1 year ago

0 Clemens Ladisch over 1 year ago

Guru 317000 points

What are the voltages at REFA and REFB?

0 Bert Thomas over 1 year ago in reply to Clemens Ladisch

Prodigy 10 points

As in the schematic above: 3.3V on the low side (refA) and the resistor is connected to +5V on the high side. However, over the capacitor C16 (and thus on the refB pin) there's a voltage of about 4.0V.

0 Joshua Salinas over 1 year ago in reply to Bert Thomas

TI__Mastermind 22910 points

Hello Bert,

What is powering up Vref_A? A power supply or an LDO? If it's an LDO can you switch to a power supply and let us know if this resolves the issue?

Regards,

Josh

0 Bert Thomas over 1 year ago in reply to Joshua Salinas

Prodigy 10 points

VrefA was powered by a LDO indeed. I removed the LDO from the PCB and connected a power supply instead and it seems to make a difference. Without load it is 3.7V and with 1.5M load it is 3.4V
All these values are not very 'firm'. They seem to change continuously, even though its only a couple of mV. I don't see that happen with normal supply rails.

0 Joshua Salinas over 1 year ago in reply to Bert Thomas

TI__Mastermind 22910 points

Hello Bert,

LDOs cannot sink current. What usually happens is the LDO charges the capacitor above the voltage supplied. That's the reason you always saw a voltage around 4V.

On your power supply, please make sure the current is not clamping. And make sure the 1.5M resistor is soldered on correctly.

Regards,

Josh

0 Bert Thomas over 1 year ago in reply to Joshua Salinas

Prodigy 10 points

I'm sorry, I don't fully understand. Could you please elaborate? I understand that a LDO cannot sink current, but it that were the problem, wouldn't the output of the LDO also be at 4V? That is not the case.

0 Clemens Ladisch over 1 year ago in reply to Bert Thomas

Guru 317000 points

During normal operation, a small current flows into VREF_B and out of VREF_A. (These are not power supply pins, but analog biasing voltages.)

An LDO cannot sink current, so if there is no other device that consumes some power on the 3.3 V supply, then the VREF_A current will charge the capacitor up to a higher voltage. To prevent this, connect a resistor of at most 470 kΩ between VREF_A and GND.

0 Bert Thomas over 1 year ago in reply to Clemens Ladisch

Prodigy 10 points

VREF_A is connected to the 3.3V supply rail (and thus to the LDO). The voltage on the supply rail does not change, it remains at 3.3V. However the 'output' side _is_ at a voltage higher dan 3.3V. Adding a 470k resistor between 3.3V and GND lowers the 'output' voltage from about 4.0V to about 3.8V.

This design has 3 LSF0108: 16 bit for address and 8 bit for data so I assume that all three add to charging the capacitor? Does that mean that the 470k must be lowered to 1/3 of that?

0 Clemens Ladisch over 1 year ago in reply to Bert Thomas

Guru 317000 points

The schematic shows separate capacitors (C17, C19). In any case, the currents out of the VREF_A pins add up, so you need three resistors, or just one smaller resistor.

The EN voltage determines the output clamping; EN is the gate of the MOSFETs, so the output clamps at about 0.7 V (V_{GS_threshold}) lower than that. The VREF_x/EN circuit ensures that the EN voltage is about 0.7 V above VREF_A. All fluctuations that you see should be mirrored at the EN pin.

Is the EN voltage stable, or is it affected by the signals?

The CY14B104 has clamping diodes at its inputs, so if the LSF outputs float higher, this will not hurt.

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LSF0108: Voltage on low side too high