SN74LVC1G125: Output rise time

Johan Gjellan

Prodigy 370 points

Part Number: SN74LVC1G125

Tool/software:

Hi team,

I have two questions on the SN74LVC1G125.

My customer have an input signal that is 3.3V LVCMOS with a 5ns rise time. What will the rise time of the output be?

The datasheet states that it is "...good for high speed applications up to 100 MHz". What is the maximum signal rate supported by SN74LVC1G125?

Best regards,
Johan

over 1 year ago

0 Ian Graham over 1 year ago

TI__Genius 9311 points

Hi Johan,

The rise time and maximum signal rate are both heavily dependent on load conditions. Without knowing the load capacitance of your system, I cannot give a specific answer about the maximum signal rate of the part. the 100 MHz described in the datasheet is based on our test load conditions, which are described in section8 Parameter Measurement Information.

Once you know your loading conditions, the process of calculating the transition rate can be found in this FAQ: [FAQ] What is the output transition rate for a logic device?

The maximum signal rate can then be estimated by 1/( 1/(Output transition rate) + Tpd )

Best,

Ian

0 Johan Gjellan over 1 year ago in reply to Ian Graham

TI__Prodigy 370 points

Hi Ian,

Thank you. I calculated for SN74LVC1G125 (assuming 50pF) and got the following:

t_t = 2.9 ns, tpd = 3.7 ns

Using your formula above for maximum signal rate gives:

1/( 1/(2.9ns) + 3.7ns) = 2.9*10^-9 Hz

Is there a typo? Should it perhaps be:

1/ (2.9ns + 3.7ns) ≈ 150MHz?

Best regards,

Johan

+1 Ian Graham over 1 year ago in reply to Johan Gjellan

TI__Genius 9311 points

Hi Johan,

Yes, that's correct.