Tool/software:
Hi Team,
I am interfacing AND gate (SN74LVC1G11DCKR) Output to a NOT gate(SN74LVC1GU04DBVR) input.
component 1 | VOH1 (min) (V) |
VOL1 (MAX) (V) |
VIH1 (MIN) (V) |
VIL1 (MAX) (V) |
Component 2 | VOH2 (min) (V) |
VOL2 (MAX) (V) |
VIH2 (MIN) (V) |
VIL2 (MAX) (V) |
Interface 1-2 Compatibility CONDITION1 VOH1(MIN) > VIH2(MIN) |
Interface 1-2 Compatibility CONDITION2 VIL2(MAX) > VOL1(MAX) |
Interface 2-1 Compatibility CONDITION1 VOH2(MIN) > VIH1(MIN) |
Interface 2-1 Compatibility CONDITION2 VIL1(MIN) > VOL2(MAX) |
SN74LVC1G11DCKR (3 INPUT AND) |
2.4 | 0.55 | 2 | 0.8 | SN74LVC1GU04DBVR (1 bit NOT) |
2.4 | 0.55 | 2.475 | 0.825 | FALSE | TRUE | TRUE | TRUE |
I see compatibility issue for 1st case.
How to approach this?
Thanks,
Vidhya