Tool/software:
I have noticed that if an input to the CD4027BF flip-flop is driven more negative than about 150mV, the device begins to draw a lot of current. In my application there is a bit of inductance in the circuit and at times a spike may appear at an input pin. When the flip-flop begins to draw current, the bias power supply powering the CD4027BF is current limited and the chip becomes latched, drawing the input voltage down to about 3 V. The CD4027BF starts getting hot as well.
I was wondering if someone could give me some insight as to why this IC latches like this under some circumstances since out customer is wanting a true root cause analysis. I realize that this is operation beyond the normal operating range of the CD4027BF.