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CD4027B-MIL: Negative spikes at input latching IC

Part Number: CD4027B-MIL

Tool/software:

I have noticed that if an input to the CD4027BF flip-flop is driven more negative than about 150mV, the device begins to draw a lot of current. In my application there is a bit of inductance in the circuit and at times a spike may appear at an input pin. When the flip-flop begins to draw current, the bias power supply powering the CD4027BF is current limited and the chip becomes latched, drawing the input voltage down to about 3 V. The CD4027BF starts getting hot as well.

I was wondering if someone could give me some insight as to why this IC latches like this under some circumstances since out customer is wanting a true root cause analysis. I realize that this is operation beyond the normal operating range of the CD4027BF. 

  • Hi John,

    This device has an internal diode from GND to the input pins to improve signal integrity. By putting a negative voltage on the input pin, the customer may by activating that diode, shorting the input to ground. This would explain the heat and current draw through the device.

    Best,

    Ian

  • integrity

    Thanks for your response. It seems that after the spike it would stop drawing current but something internally latches to keep the current .flowing in the input power pins. This draws down the Bias supply for the chip and the entire circuit stops functioning. I guess I need to know why it latches this way. Another engineer here said that he had seen this before a few years previous but didn't know what internal workings made it latch. 

  • Latch-up can happen when you exceed the absolute maximum ratings, i.e., when the voltage is less than −0.5 V with a clamping current larger than 10 mA. See the Latch-up White Paper.

    External clamping diodes might help.

  • Thank you. This solved my issue. At least I can now provide a somewhat intelligent response to why the latching occurs. Wasn't aware of the White Paper at all.