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SN74LVC125A: maximum voltage for the 4-fold gates SN74LVC125A

Part Number: SN74LVC125A
Other Parts Discussed in Thread: SN74LV125A

I would like to use the SN74LVC125A (SN74LVC125ABGAR or SN74LVC125AWBQARQ1) in a new project instead of the SN74LVC1G125.

However, there is a discrepancy in the data sheets regarding the maximum voltage that can be applied to the outputs in the high-impedance case.

For the single gates, a maximum voltage of 6.5V is explicitly defined for the high-impedance case, but this entry is missing for the 4-fold gates. (see pic 01.jgp )

With the planned circuit, however, we would be dependent on the fact that the output of the gate can be charged with up to 5V (i.e. higher than the planned VCC of 3.3V) in the case of high impedance.

 

The further information in the data sheet may indicate that this may have been inadvertently omitted.

Can you please confirm whether the missing specification of the maximum voltage at high-impedance is an error in the data sheet, or whether the 4-fold gate actually deviates from the behavior of the single-gate IC in this respect?

Perhaps the exact same single gate is four times built into the SN74LVC125A (exact same process…is this the case or not ??)

 

Single-gate IC: in the Max ratings there is the pointOutput voltage at Tristate max. 6.5V: (this point is also listed in most data sheets of the LVC series)

(https://www.ti.com/lit/ds/symlink/sn74lvc1g125.pdf)

See pic 01.jgp

 

However, this entry is missing for the 4-way gates SN74LVC125A, so the outputs should only be charged up to VCC+0.5V:

(https://www.ti.com/lit/ds/symlink/sn74lvc125a.pdf)

See pic 02.jgp

 

However, according to a TI forum post, the specification of the Output Clamp Current indicates that it should be the same here as with the single-gate IC.

(https://e2e.ti.com/support/logic-group/logic/f/logic-forum/936385/faq-can-you-pull-up-an-open-drain-output-to-a-higher-voltage-than-the-device-s-supply-vcc-voltage/3458615#3458615)

Thanks

Rolandpic 01.jpgpic 02.jpg