SN74AUC1G74 Jitter

Inderjit Bains

Other Parts Discussed in Thread: SN74AUC1G74

I'm looking at using the SN74AUC1G74 in a divide-by-two application. With a 50MHz, 6.5ns rise/fall time input, what is the worst-case output jitter? VCC for the SN74AUC1G74 is 1.3V, input is driven to 1.8V (so the rise/fall time should be a bit better than 6.5ns at 1.3V).

over 12 years ago

0 Chris Cockrill over 12 years ago

TI__Mastermind 46480 points

Generally we do not take jitter dat for standard logic devices. LVC family had a typical jitte of about 20ps. I suspect AUC would be as good or better.

Keep in mind that when you use a flip flop as a divide by 2 the jitter will actually get better.

0 Inderjit Bains over 12 years ago in reply to Chris Cockrill

Expert 2745 points

Question on timing (p. 4 of the SN74AUC1G74 datasheet), connecting nQ to D, input to CLK: at 1.2V, the required hold time for D is 0.5ns. The minimum propagation time from CLK to nQ is 1ns. Is the 0.5ns margin enough for -40C to +85C? There will be no other connections to nQ and D, and the pins are next to each other on the package.

0 Chris Cockrill over 12 years ago in reply to Inderjit Bains

TI__Mastermind 46480 points

Hi Inderjit

The specs in the datasheet are across temperature and process unless noted otherwise. So yes the spec is good across temp.

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SN74AUC1G74 Jitter