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SN74LVC2G02 power-up behaviour

Erik Boogh
Prodigy 10 points

My application requires that the output of the NOR gate will not exceed 1V during power-up.
The output is pulled-down to GND (R=200kOhm)

Inputs during power-up:
Input 1 is pulled-up to VCC (R=5kOhm)
Input 2 can be low or high (undefined, but not floating)

I figured that an input level of 1V is able to turn on the low-side FET of the input buffer even if the supply voltage is lower than the minimum of 1.65V (Uhigh_min at 1.65V is approximately 1V).
If the internal logic is also functioning at 1V or at least before the output buffer is able to drive the pull-down above 1V, everything should be OK.

Is it possible to guarantee a low output state during power-up (for VCC > 1V and output pulled down)?

  • 0
    TI__Mastermind 46480 points

    at about 1v the part will turn on and begin to function properly. so if you see a rise on the output at power up it is usually no higher than 0.8V.  Since the Vcc is so low at this time there is not much drive so the output can be overpowered by a week pulldown. If the output is pulled down you should see no rise.