I'm using SN74AHC16374 in a new design. In the application there is a risk (based on min/max timing of the logic driving the device) that a runt clock pulse of less than the minimum specified (5.5ns) would be seen. I would not expect to capture data on that runt pulse and there would be several hundred clock pulses which exceed the minimum pulse duration following it before I wanted to capture data.
Is the effect of these runt pulses known? i.e. does it just make the data output indeterminate and can I be sure that the subsequent clock edges will capture data?
Thanks, Richard.
