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SN74AUP1G79 power up state

Ryan May
Genius 13700 points
Other Parts Discussed in Thread: SN74AUP1G80, SN74AUP1G79, SN74AUP1G74, SN74LVC1G373

Hello,

I am working with the SN74AUP1G79 / SN74AUP1G80.

I need to know that if I have CLK and D pulled low through pull down resistors.  Will the output always (I mean 100% of the time) go to a logic high when power is applied?

The function table on Pg. 2 would suggest is goes to Q0 but that state is not described anywhere in the datasheet.

My first thought is that using a pull-up on Q would assure this since Q is most likely to start up in a High-Z state.

  • 0
    TI__Genius 9860 points
    Hi Ryan, the output at power-up is unknown. We have seen that although most of the time the Q output is low upon power-up, this can vary widely across temperature, lot, and voltage levels.

    If you need a specific state on power-up, you should avoid reading the output until the first valid clock edge after VCC reaches the recommended level. You can also switch to a part with clear and preset pins that can guarantee a specific output (SN74AUP1G74).

    We actually just released an app note on this topic after customer concern: www.ti.com/lit/an/scha005/scha005.pdf

    Regards,
    Ryan
  • 0 in reply to C. Ryan Land
    TI__Genius 13700 points
    Hello Ryan,

    Thanks for the response.

    Do you think using the SN74LVC1G373 and the OE function with a pull up would accomplish the high-state start-up case?

    This only solves the first step of the design constraints. I am looking for a device that always powers up to a logic 1, and then through whatever mechanism (clock edge, set, reset, latch enable, ………) can be set to a logic low (and only to a logic low) and remain a logic low with no means of ever setting it high (except for removing and reapplying power).

    While the case described above is a little odd the only solution that I can think of that could accomplish this is using a pull-up resistor and an SCR to short to ground.
  • 0 in reply to Ryan May
    TI__Genius 9860 points
    You could try a D flip flop with D to GND and a /PRE pin pulled up to VCC. The MCU could drive /PRE low to allow that high state at the output. Once PRE is released, there would never be a 1 at the output again if a clock is present (since D would be shorted).

    You say "no means of ever setting it high." Do you mean you want some case where it's physically impossible to set it high? Or that it can just be done with one pulse or something? Maybe understanding the full application, and why the high output is unwanted after the initial state, would help me better.
  • 0 in reply to C. Ryan Land
    Prodigy 10 points

    Hi,

    I have some question to SN74LVC1G373 at power up. At that moment I have sequence:

    OE=LOW; LE=LOW, D=LOW and OUTPUT=HIGH

    That is the problem - I need to have LOW at the OUTPUT. I tried to set OE=HIGH for 10ms and indeed OUTPUT was LOW (eactly Hi because latch is pulled down by 10k). When I released OE then OUTPUT jumped to HIGH. I was looking for some peaks in OE, LE and D and didn't find any. If I set LE to HIGH at startup and keep OE=LOW, D=LOW then i have output low.

    Is this latch working in that way? Always have HIGH at the ouput after startup?

    Best Regards

    Krzysztof

  • 0 in reply to user4886814
    TI__Guru* 96862 points
    Hi Krzysztof,

    As Ryan stated above, the output of the device is unknown at power-up. Only after a valid clock pulse has been detected will the output state be defined.