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CD4025B - unused gates in the same chip

Other Parts Discussed in Thread: CD4025B, CD4053B, CD4066B, CD4052B, CD4051B, CD4016B

Does the CD4025B NOR gate chip use "FET switch-type functions" where the unused gates do not have to have their inputs tied high or low?

I read your recommendation on tying unused inputs high or low, even on unused gates inside the same chip, but there was this exception for logic gates that use FET switch-type function.

I'm only using one of the NOR gates inside of CD4025B (3-inputs, 3 NOR gates). 

It looks to me that the CD4025B used FETs all thru this chip.

Do I have to tie the unused inputs high or low on the unused gates?

  • Hi Jim,

    I would always advise to tie the unused inputs to gnd to prevent the pin picking up unwanted signals to cause output logic to change .
  • I'm not going to be using the outputs of the unused gates. Therefore, why is in necessary to tie the inputs of the unused gates high or low?
  • I have personally experienced cases where floating CMOS inputs on unused gate sections caused malfunction of the other gates in the IC that were in use. This is especially the case with 4000B series logic. A common result of a floating input would be intermittent circuit operation. Periodically the system would randomly malfunction. Raising your hand up and down above the circuitry (2 to 5 inches at 1 or 2 second rate) could cause the system to go in and out of proper operation. This is a great debugging tool when you are stumped by random malfunctions, but may lead to suspicious looks from co-workers.

    The reference to "switch" input types in the logic family notes that you refer to should really be phrased as "analog switch" type inputs. Examples of this are the analog I/O pins on CD4016B, CD4051B, CD4052B, CD4053B, CD4066B and other related analog signal transmission gate devices. The control inputs (Select lines) on those devices must be committed high or low; but the transmission I/O pins of the analog switches can float without issue. BTW note that on CD4016 and CD4066 the select input lines go rail-to-rail (VDD to VSS), but on the CD405x series the select lines go from VDD to GND and not to VSS - the negative supply.

    To directly answer your original question. --> Always tie the inputs of unused gates to ground or VDD. <--

    Additional tip... It is fine to tie the unused inputs to a rail through a resistor (of any value) so you can patch in the unused gate at a later time. Otherwise the input pin may be difficult to access due to a direct connection to the supply rail. If the input is tied to GND or VDD with a direct path such as the plated through hole of the pin, it becomes very difficult to access. This would commonly be the case with the original through-hole DIP versions of the part.
  • Hi Jim ,

    Good question. Even though you are not using either the inputs or outputs , the floating inputs can cause the Icc current to be many times the regular Icc current , depending on the inputs picking up the random voltage . The high Icc currents might be over the abs max current which the device can handle and can result in thermal breakdown of the part in extreme cases too  .

    The below app note also explains further on the effects of floating inputs .

    slownfloatingCMOS_scba004c.pdf