Does the CD4025B NOR gate chip use "FET switch-type functions" where the unused gates do not have to have their inputs tied high or low?
I read your recommendation on tying unused inputs high or low, even on unused gates inside the same chip, but there was this exception for logic gates that use FET switch-type function.
I'm only using one of the NOR gates inside of CD4025B (3-inputs, 3 NOR gates).
It looks to me that the CD4025B used FETs all thru this chip.
Do I have to tie the unused inputs high or low on the unused gates?