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SN74CB3Q3345 Partial Power Down Isolation

Other Parts Discussed in Thread: SN74CB3Q3345

Question regarding SN74CB3Q3345 in partial power down:

When Vcc, OE, and OE/ are 0V, is there isolation between the A and B lines?

The notes about partial power-down are vague and I can't determine if there is isolation during partial power down or if the device is just not damaged. I don't know how the "off" state is defined.

Do you have an approximation or order of magnitude for this isolation?

Thank you,


  • The datasheet says:

    This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

    The maximum leakage current is specified as Ioff in the datasheet.

    SCEA026 (Logic in Live-Insertion Applications With a Focus on GTLP) shows on page 5 how Ioff can be implemented in families other than GTLP:

    … the back gate is blocked with a diode to prevent excess currents flowing from the external pin to VCC when the output voltage is greater than VCC by at least 0.7 V.
  • Thank you Clemens for your contribution .
    Yes , there is internal Ioff protection circuitry which isolates the inputs / outputs from Vcc to prevent current flowing back into Vcc and accidently turning on the system . Some of the devices which do not have Ioff protection have the 'accidently powering on without power supply' problem due to this exact reason .