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SN74AUP2G14 hysteresis variation over time

Yan Drolet
Prodigy 90 points
Other Parts Discussed in Thread: SN74AUP2G14

Considering that the supply voltage and the temperature are fixed and have zero noise, what is the variation of "VT+ max" or "VT- MIN" over time ? 

  • 0
    TI__Guru* 92935 points

    Looks like your question might be around Logic so moving this to our Logic forum.

  • 0 in reply to Blake TI Community
    TI__Guru 61690 points
    Hi Yan ,

    It is guaranteed to not violate the datasheet specs.
    TI doesn't spec the variation of threshold voltage over time. given the ideal conditions , it should not vary .
  • 0 in reply to ShreyasRao
    Prodigy 90 points

    Hello ShreyasRao

    Thanks for your response.

    Can TI provide the hysteresis variation from chip to chip for a specific condition ?

    In my design, when i swap multiple SN74AUP2G14 on the same circuit, i measure major differences in between them. In order to qualify my design for production i would need to confirm the maximum deviation from one chip to an other chip for a fixed temperature and supply. I would also like to point out that the soldering/de-soldering process in between the tests does not affect the measurement when I re-solder the same chip in the circuit.

    Thanks

    Yan 

  • 0 in reply to Yan Drolet
    TI__Guru 61690 points
    Hi Yan ,

    There could definitely be variations ,however it is guaranteed not to violate the datasheet specs . Do you see them violate the specs given ?
    The min max are given to account for all the variations the device passes through in its development stage from sand to silicon.
  • 0 in reply to ShreyasRao
    Prodigy 90 points

    They don't violate the spec, but since the spec include all environment changes in the same value, it is very difficult to extract for example the supply effect on that value. Could you provide the supply voltage effect on V hysteresis separately from the other effect ?