SN74HC165: malfunction depending on rise time clock signal

Martin Grimmer

Part Number: SN74HC165

Hi,

we have malfunction of SN74HC165PW while using it with Vcc=5V, clock-signals of 1kHz and rise time to 50% of Vcc is about 80µs.

With rise time to 50% of Vcc of about 9µs it works fine.

Is there any requirement for the rise time, or do you see another root cause?

over 8 years ago

0 Clemens Ladisch over 8 years ago

Guru 316440 points

The allowed input rise time is specified in section 6.3 of the datasheet. Your 32000 ns/V is a little bit too slow.

If you cannot change the clock source, add a Schmitt-trigger buffer.

0 Emrys Maier over 8 years ago

TI__Guru* 97046 points

Hi Martin,

There's an input timing requirement spec listed in the Recommended Operating Conditions table of the datasheet. With a Vcc of 5V, you shouldn't exceed 500ns per volt (ie 2.5us for 50% Vcc or 5us for the full rise time).

CMOS inputs are very sensitive to slow edges and can produce internal oscillations, excessive current, and erratic behavior. We have an application report on this topic that's an interesting read:

Implications of Slow or Floating CMOS Inputs (Rev. D)

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SN74HC165: malfunction depending on rise time clock signal