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SN74LVC16244A: Decoupling and rise fall times with LVDS301 as load

Felix Risch25
Intellectual 1110 points
Part Number: SN74LVC16244A
Other Parts Discussed in Thread: SN65LVDS301

Hello team,

my customer is asking for the decoupling caps of the SN74LVC16244. As it has 4 supply pins, the recoommendation is:

"For devices with a single supply, 0.1uF is recommended. If there are multiple VCC pins, then 0.01 or 0.022uF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1uF and a 1uF are commonly used in parallel.

In my opinion, the statement is not clear, as all LVC16244 have in total 4 supply pins. What is the recommendation? Use at each pin 0.01u to 0.022u cap and then paralell them with 0.1uF each?

Another point is the rise and fall times of the device. The LVC16244 is driving the input pins of the SN65LVDS301, with an input capacitance of 1.5pF. Do you have a quick estimate of the rise and fall times?

Thank you very much and kind regards,

Felix

  • 0
    TI__Guru* 97046 points

    Hi Felix,

    You might notice that the same statement is on the vast majority of logic datasheets -- many of those only have a single supply pin, but some have multiple supply pins. It would be ideal if the statement were tailored to each device, but that's not how it was done.

    Since the SN74LVC16244 has 4 supply pins, the recommendation is clear: If there are multiple VCC pins, then 0.01 or 0.022uF is recommended for each power pin.

    I would expect to see around 1 ns for the rising edge for such a light load.