Hello Team,
In my design i am using a total of 36 voltage translators. Whenever the signal is driven from the voltage translator to the FPGA we are observing non monotonic signal rise at the thresholds. By adding series termination resistor we can overcome this issue, but doing so will increase the resistors count and complexity(density) of the design. So kindly provide a solution on this issue. Also we suspect the model kindly have a through check on the same.
Regards,
Karthik M B
