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Dear team,
Could you kindly help confirm if it is OK that the output of channel 1 as the input of channel as below schematic shows?
Thanks.
Best regards,
Sammi
This is a perfectly valid way of constructing a three-input AND gate.
What is withh all those RC filters? A time constant of 1 ms will exceed the input transition rise rate limit of 200 ns/V. Such slow edges requires AND gates with Schmitt-trigger inputs, i.e., 2× SN74AUP1G97.