CD4046B: Use PLL CD4046B and frequency divider CD4040B to design a 60Hz frequency tracker

Hello,

Were you able to get your system designed?

Building a PLL for 60 Hz should be relatively easy with the components you have selected.  The diagram you provided is a good starting point.

My recommendation would be to first very carefully read the entire datasheet for both devices. I know that this is tedious, but these are complex devices and there's a _ton_ of useful info in the datasheets. The additional datasheets others have provided are also useful resources, as the '4046 function is pretty much the same for any logic family or manufacturer.

First you need to select your supply voltage and VCO operating frequency, which is going to be related to your desired lock frequency and the size of your counter. I'm going to assume 5V since that's a very common operating voltage and might allow you to select other parts that are more modern later (CD4k logic is quite old and optimized for 15V operation, which doesn't work with any other logic family).

The VCO lists a minimum 'max operating frequency' of 300 kHz (0.3 MHz) at 5 V with a 10kohm R1. This spec can often be confusing -- the meaning is that the output frequency will _definitely_ be able to hit 300 kHz, however beyond that we cannot guarantee that the oscillator will work -- the typical max at 5V is 600 kHz.

Looking at figure 4 in the datasheet, you can see the RC values required at 5V to set the VCO to 60 Hz directly:

Based on this, I don't think you really need the counter.  You _could_ set the frequency up to ~120 kHz, and then divide it back down again to 60 Hz, but why do that when you can just configure the CD4046B directly to operate at 60 Hz?

You can set the timing values as given above - R1 = 1 Mohm, C1 ~= 0.08uF (80nF).  Typically prototyping is the best way to check out these circuits -- just hook them up with 'close' values and then adjust as needed to get your final frequency range on the bench. You can also add an offset with R2 = 1 Mohm to try to narrow the operating frequency range, but most likely that won't be required and you can just leave R2 as open circuit.

The biggest problem with this particular application is that the 60 Hz signal is very slow, so your response time of the PLL will also be relatively slow. It probably won't matter though, since I'm guessing you are trying to match phase with a power signal, and those don't have fast fluctations in phase or frequency.

I would recommend using 100kohm and 10uF for your low pass filter out of the phase comparator of your choice (PC1 will give you a 90 degree phase difference, PC2 is going to be phase matched). These values give a cutoff frequency of ~0.2 Hz, which will be relatively slow to respond, but will stabilize the VCO well.

Hi Sk,

The low pass filter values will impact the capture range which can be seen on page 3-125 of the CD4046B. The note also provides some literature that goes into great detail on the control theory behind it. 

This capture range will be less than or equal to the lock range and will determine the range of frequencies the PLL can lock to if initially out of lock. 

Also, I'm glad to see the real world testing is working as planned.