Hello,
I have a problem with my SN74V293 FIFO. I'm not able to readout the memory although I use the timing information for the clock and signals from the data sheet. The inputs of the FIFO are connected to the outputs of a 12-Bit ADC (D0 is LSB of ADC).
!LD is low during master reset. I don't use the programmable offset flags.
!BE, !OE, FSEL0, FSEL1, IP, IW, OW, PFM are always low.
!PRS, !RT, !SEN, RM are always high.
Thereby I use the FIFO with the following configuration: Normal latency, no retransmission, big-endian operation, always output enabled, noninterspersed-parity mode, 18-bit bus width for I/O.
This is my write-cycle after master reset:
The !EF is high after the first data input.
This is my read-cycle:
I would have expected to see the signal of D0 from the write-cycle at the output Q0. Additionally, I checked the behaviour of the flags !EF and !FF. They works as desired.
Do any of you have any idea where my mistake is? Did I do something obvious wrong?