LSF0204D: The propagation delay of LSF0204DRUTR

Chun-Chen Liu

Prodigy 30 points

Part Number: LSF0204D
Other Parts Discussed in Thread: LSF0204, TMUX1574, SN74AXC4T774

Hi Texas:

We would like to know the propagation delay of LSF0204DRUTR

I also checked the former issue page "LSF0204: Propagation delay of LSF0204RUTR"

You said that the load capacitance and resistance and any pullup resistor will impact the propagation delay

Because our SPI topology Tclk frequency is 66MHz and the delay time budget of level shift element need to be 1ns or at least below 1.5ns

From VDD 1.8V to VDD 3.3V, our P3V3 pullup resistor is 10K and no load capacitance and resistance

Can this level shift meet time delay requirement?

Thanks

Nick

over 4 years ago

0 Rami Mooti1 over 4 years ago

TI__Mastermind 35648 points

Hey Nick,

Can you specify what you mean by no load capacitance or resistance? Is this simply floating or is it connected into another device? This devices pin will still have some load. Depending on the load you can estimate whether this should work.

I would advise to watch this training video which covers up translation with the LSF family of devices. It also covers the equation and has an example for balancing the pull up resistors with the data rate

https://training.ti.com/translation-lsf-family-0?cu=1134826

Thanks,
Rami

0 Chun-Chen Liu over 4 years ago in reply to Rami Mooti1

Prodigy 30 points

Hi Rami

Thanks for your information, I have watched the video

But it still can't solve this issue

Here is our block diagram of SPI, the series topology only put 10K pullup resistor on the B-side of level shift

How to evaluate the delay time of level shift? Can it at least below 1.5ns?

Thank you

0 Clemens Ladisch over 4 years ago in reply to Chun-Chen Liu

Guru 322020 points

This depends on the total capacitance on the entire signal line. Longer traces and more devices increase the capacitance.

We do not know your board, so it is impossible to estimate. The best way to find out is to look at the actual signal shape with an oscilloscope. If the rising edges are too slow, you have to use a stronger pullup at B1 (which requires more drive strength from the CPU).

0 Chun-Chen Liu over 4 years ago in reply to Clemens Ladisch

Prodigy 30 points

Hi Clemens

I got your suggestion, we will use the oscilloscope to correlate our evolution if need in next stage

And I really need the propagation delay of level shift to make sure the 66MHz SPI topology is safe in the early stage.

For example, the demux is also TI product, there are propagation delay in TMUX1574 data sheet

And I can find delay time of all element in our topology but LSF0204DRUTR

If propagation delay of LSF0204DRUTR is larger than 1.5ns, we will change it in the early stage

Thanks

0 Clemens Ladisch over 4 years ago in reply to Chun-Chen Liu

Guru 322020 points

Under the test conditions specified in section 7.8 of the datasheet, the typical propagation delay is less then 1.5 ns, but the maximum is not.

With 10 kΩ, rising edges will be slower.

The fastest alternative is the SN47AXC4T774. It is a buffered level shifter, so it is slower.

0 Chun-Chen Liu over 4 years ago in reply to Clemens Ladisch

Prodigy 30 points

Hi Clemens

Can you provide the "test conditions specified in section 7.8 of the datasheet" and "data sheet of SN47AXC4T774"?

Thanks

0 Rami Mooti1 over 4 years ago in reply to Chun-Chen Liu

TI__Mastermind 35648 points

Hello,

From the datasheet

and to help define tplh, tphl, tplz and tpzl for you :

There was a typo in the part number for the AXC part. 47 should be 74.
The part Clemens is referring to is the SN74AXC4T774
Here is the datasheet

Thanks,
Rami

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LSF0204D: The propagation delay of LSF0204DRUTR