Hi team,
Our customer's circuit structure is a front-end FPGA + CCD signal level translator IC + back-end IC. The CCD signal from the FPGA is a 3.3-V level signal that requires a 3.3V->5V level translation of the CCD signal. The CCD clock frequency is 35MHz, and the input capacitance of the back-end IC clock pin is 350pF. The CP and RS signals are also frequency 35MHz, but the pulse width is one quarter of the cycle, and the CP and RS pins of the back-end IC have an input capacitance of 20pF. The effect of IC transmission delay on the overall drive signal timing needs to be considered.
Is there a suitable level translation IC recommended? I found the LM98555 CCD driver IC on TI's official website, but it only works at 30MHz. Do you have any other solutions
Best Regards,
Amy