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3.3V to 1.8V level shifter for 29 inputs

Hi Team,

I'm currently supporting a customer on this thread: https://e2e.ti.com/support/interface/f/138/t/732240 

He's using our SerDes to interface with an FPGA. The issue is our SerDes is a 3.3V device while his FPGA requires 1.8V. Therefore, he needs to shift the voltage down from 3.3V to 1.8V for 29 inputs (28 data bits + the clock). The data rate would be in the range of 20 to 85 Mbps for each input. Can you recommend a device suitable for this application?

Regards,

I.K. 

  • Hi I.K.,

    There are quite a few parts that could achieve this.  If they are looking for something in a single package, my first choice would be SN74LVC32245.  There are also 16-bit and 8-bit versions if it would be preferable to spread the channels around the board a bit more.

    The LVC family has over-voltage tolerant inputs, so you just supply it with 1.8V and then input 3.3V to get output 1.8V.

  • Hello,

    Thanks for the additional information. In looking at the Data Sheet for the SN74LVC32245, the tsko parameter is 1ns. I assume that this means that the skew between all pins is less than 1ns. Is this correct? I have a 28 bit data bus along with a data clock, I want to make sure that the skew between all the bits / clk going though the device is small enough that I can re-register them to the clock when they get into the FPGA.

  • Hi Ken,

    Yes, that's exactly what the skew means.  It's typical for logic parts to have well under 1ns of skew, but most are rated to 1ns max.  If you have channels that are particularly susceptible to timing differences, I would recommend placing them on adjacent channels.

    Also, the 1ns skew is only for a single device, channel to channel.  If you use two devices, we can't guarantee the channels will match up perfectly.

  • Thanks Emrys, I need to level shift the DS90CR288, so this part will be perfect, I can level shift the entire part with the SN74LVC32245, and maintain matching. Thanks Again!