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SN74LVC1G123: Output Q behavior

Part Number: SN74LVC1G123
Other Parts Discussed in Thread: SN74LVC1G34, SN74LVC1G17

Hi,

There are times when Q does not respond to the CLR signal.
Could you check the following waveform?



CH1:A, CH2:Rext/Cext, CH3:CLR, CH4:Q
B signal is fixed at H level.

When CLR is fixed at H, Q responds to the A signal.


Is there any reason?
Please give me your advice.

Best regards,
Yuto Sakai

  • Hi Yuto,

    Could you attach a copy of your schematic here as well?

    Thanks!

    Chad Crosby

  • Hi Chad-san,

    Thank you for your reply.
    Please check the schematic attached.


    Best regards,
    Yuto Sakai

  • Hi Yuto,

    After looking at your waveform a bit more, I noticed that the time scale for it is 1s. What is the rise/fall time of the CLR waveform?

    While A & B have Schmitt Trigger inputs, and do not need to conform to https://www.ti.com/lit/an/scba004d/scba004d.pdf, the CLR pin is a regular CMOS input, and will need to follow these recommendations.

    Thanks!

    Chad Crosby

  • Hi Chad-san,

    Thank you for your reply.
    I have checked the application note.
    I thought that what was written was that slow or floating inputs would lead to damage to the FET.

    Therefore, I did not think that the operation of the IC is not guaranteed.
    As long as the FET is not broken, I think that the expected operation can be seen at the timing when it exceeds the threshold.
    Is there any other reason for the operation of output Q in the above post?

    I'm confirming the rise/fall time of CLR.

    Best regards,
    Yuto Sakai

  • Hi Sakai-san,

    My only other concern is how noisy the input signals are. Since A is a Schmitt Trigger input, the noisiness on that input will be fine, It's just a little concerning for the CLR input.

    Other than that, I'll wait to hear back about the rise/fall time.

    Thanks!

    Chad Crosby

  • Hi Chad-san,

    The waveform of CLR is acquired.
    The rise time is 605ns and the fall time is 6.746ns.
    A signal with no noise is input.




    Could you comment on the operation of Q based on this waveform?

    Best regards,
    Yuto Sakai

  • Hi Sakai-san,

    Yes the rise time of the input signal is definitely too slow. It might help to look at the datasheet for the SN74LVC1G34: this should provide a bit more detail of the input requirements the CLR pin will have.

    From the SN74LVC1G34's datasheet, you'll need an input signal with a rise time of 10ns/V.

    It's also hard to tell here, but you'll need to make sure that this signal rises above the VIH spec (0.7 * 5V = 3.5V) in order for the device to recognize it as a logic high signal.

    A possible solution to this: You could use a SN74LVC1G17 in series with the CLR pin to handle the slow inputs.

    Thanks!

    Chad Crosby