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How to select an appropriate level translator?

Adam Gropp
Prodigy 130 points
Other Parts Discussed in Thread: MAX232, SN74LVC1G34, SN74AHC1G125

Hello, I am needing help selecting level translator for a project. I want to take the output signal (TX) from a MAX232 chip and input the signal to my FPGA (Xilinx KC705 eval brd). It is my understanding that the output of the MAX232 chip is 5V TTL logic. I do not believe that my FPGA pins support 5V TTL.  I have seen different types of level shifter (voltage and mixed signal). I want to target IOSTANDARD LVTTL or LVCMOS on the FPGA pin. It is my understanding that if I use LVTTL/LVCMOS standard then my input signal needs to comply with LVTTL/LVCMOS standard. I feel like I need a level shifter that will convert from 5V TTL to 3.3V TTL ( which I believe is LVTTL). Could help me gain a better understanding on how to select the correct product? Thank you for your time.

Adam

  • 0
    TI__Mastermind 29925 points
    Hello Adam,

    In order to help you select an appropriate translator we need some more information from you. Is your application open-drain or push pull? What is your maximum data rate? Do you know what kind of drive strength you will require?
  • 0 in reply to aozer
    Prodigy 130 points
    Hello aozer,

    I am not sure whether the MAX232 chip is open drain or push pull. I do not see this spec. in the data sheet. It just states that the receiver converts from EIA-232 to 5V TTL/CMOS. The chip is a TI product MAX232n. As far as the FPGA. The input uses a single ended CMOS buffer for LVTTL standard and a push-pull CMOS buffer for the output. A drive strength of 12mA. The maximum data rate is 120kbs as the MAX232 chip supports.

    Also, I will want to output this signal from the FPGA to the MAX232 chip. So the FPGA output will be push-pull, and I will use a drive strength of 12mA. Same data rate (120kbs).

    I hope that I have given you the information that you requested. Thank you for your time.

    Adam
  • 0 in reply to Adam Gropp
    Guru 316440 points

    The switching levels of various logic standards are shown on page 4 of the Logic Guide (SDYU001). Please note that 5-V TTL and 3.3-V LVTTL use almost the same levels.

    You can connect the FPGA's LVTTL output directly to the MAX's TTL input.

    An unloaded TTL output has a voltage of about 3.7 V. If the FPGA allows this voltage, you can connect the MAX's TTL output directly to the LVTTL input.
    If not, use a buffer with a 5V-tolerant input, such as the SN74LVC1G34/125 or SN74AHC1G125. (Or simply use a 10k series resistor to limit the current through the input's ESD protection diode, but that is a hack.)