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TMS570LC4357: EMIF Performance for SRAM

user5177971
Prodigy 90 points
Part Number: TMS570LC4357


I want to use a very fast 8-10ns Async SRAM with the TMS570LC4357 and want to have the maximum Performance.

What is the maximum EMIF CLK for use with Async Memories (150MHZ like VCLK3?) (for SDRAM i assume it is 100MHz)

In Table 6-36: Emif Asynchronous Memory Swiching Characteristics of the datasheet the following Symbols are used
RS --> read Setup
RSt --> Read Strobe
RH --> Read Hold
with the footnote 1 it es referenced to SPNU563 for the ranges (e.g RS[16-1])))
But in SPNU563 in Table 21-29 the Value Range vor R_SETUP 0-F minus one Cycle

I assume, when setting R_Setup, R_Strobe and R_Hold to 0 in the Async Configurtion Register the Resulting times are
RS =1, RSt=1 and RH =1

See also Mail from Haixiao an Dec8,2010 3:25 pm
e2e.ti.com/.../83030

I think without using the strobe mode this time could not reduced. Right?

Could the strobe mode help to increase the EMIF performance in such a case?

  • 0
    TI__Guru**** 198766 points

    Hello,

    You are correct. The minimum EMIF cycles for read setup/strobe/hold is 1. The value in CExCFG is setup/strobe/hold cycles-1. The maximum EMIF clock for LC43x  is 100MHz. The EMIF clock is driven by VCLK3.

    In select strobe mode, the CS signal functions as a strobe signal, active only during the strobe period of an access. Using select strobe mode can increase the EMIF performance.

  • 0 in reply to QJ Wang
    Prodigy 90 points

    Hi QJ,

    i have some question for clarification:

    1. the Maximum EMIF Clock for LC43x is 100MHz for Async and SDRAM devices?

       (VCLK3 is specified with 150MHz and in Table 6-38 10ns(100MHz) for synchronous Memory), but for the Asynchronous i have not found a requirement in the datasheet)

      I ask esspecially because 100 MHz on VCLK3 are only achievalbe if HCLK is 100MHz (which would reduce the overall performance)

    2. The Setuptime tsu(EMDV-EMOEH) (No. 12 in Table 6-35) (11ns )is for our application very long. What are the main drivers for this requirement (High Temperature, Voltage Levels,..)

    regards,

  • 0 in reply to user5177971
    TI__Guru**** 198766 points

    Hello,

    1. Yes, the 100MHz EMIF Clock is for both sync and async logics. The EMIF_CLK is the output of EMIF clock for the external sync memory devices, but the async memory devices don't require the clock input. The data/addr/control signals for sync memory and asycn memory are synched to EMIF clock.

    It is not always possible to run each clock at its maximum frequency as GCLK must be an integral multiple of HCLK and HCLK must be an integral multiple of VCLKx. Depending on the system, the optimum performance may be obtained by maximizing either the CPU frequency, the level-two RAM interface, the level-two flash interface, or the peripherals.

    If GCLK is 300MHz, the achieved maximum EMIF clock is 75Mhz.

    2. Not sure which one is the main driver.