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TMS570LS3137: Bootloader transition to App triggers prefetchAbort

Greg Baghdikian
Prodigy 130 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm working on a TFTP bootloader for the TMS570LS3137. I'm able to successfully transfer the Application bin file over the network to the MCU where it is flashed to 0x0020020. I have set up the App linker script accordingly.

However, the App fails somewhere in the _c_int00() function. Interestingly, when I add a breakpoint to the first call in _c_int00() and step through the code from there, it does actually make it to the App (RTI LED blink code).

Any ideas as to why this is occurring?

I have attached my linker script files and my bl_config.h file.

Thanks

/*----------------------------------------------------------------------------*/
/* sys_link.cmd  (Application Linker CMD)                                                             */
/*                                                                            */
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
    VECTORS (X)  : origin=0x00020020 length=0x00000020
    FLASH0  (RX) : origin=0x00020040 length=0x0001FFC0
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0003EB00

/* USER CODE BEGIN (2) */
/* USER CODE END */
}

/* USER CODE BEGIN (3) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0
    .const   : {} > FLASH0
    .cinit   : {} > FLASH0
    .pinit   : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
    

/* USER CODE BEGIN (4) */
/* USER CODE END */
}

/* USER CODE BEGIN (5) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (6) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------*/
/* sys_link.cmd      (Bootloader)                                                         */
/*                                                                            */
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* USER CODE BEGIN (2) */
    VECTORS    (X)   : origin=0x00000000 length=0x00000020 vfill = 0xffffffff
    FLASH0     (RX)  : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff
    FLASH1     (RX)  : origin=0x00200000 length=0x00200000 vfill = 0xffffffff
    RAM       (RWX)  : origin=0x08002000 length=0x0007E000
    STACK      (RW)  : origin=0x08000000 length=0x00002000

#if 0
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00002000
    RAM     (RW) : origin=0x08002000 length=0x0007e000

/* USER CODE BEGIN (3) */
#endif
#if 1
   ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
                   length=(size(VECTORS) >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=VECTORS}

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

    ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1)  >> 3))
                   length=(size(FLASH1)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH1 }
#endif
/* USER CODE END */
}

/* USER CODE BEGIN (4) */
ECC
{
    algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH0 | FLASH1
    .const  align(32) : {} > FLASH0 | FLASH1
    .cinit  align(32) : {} > FLASH0 | FLASH1
    .pinit  align(32) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

/* USER CODE BEGIN (6) */
    flashAPI:
    {
       .\Boot\Fapi_UserDefinedFunctions.obj (.text)
       .\Boot\bl_flash.obj (.text, .data)
       --library= "c:\ti\Hercules\F021 Flash API\02.01.01\F021_API_CortexR4_BE.lib" (.text, .data)
    } palign=8 load = FLASH0 |FLASH1, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)
/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

    /*****************************************************************************
*
* bl_config.h - The configurable parameters of the boot loader.
* Author    : QJ Wang. qjwang@ti.com
* Date      : 5-25-2019
*/
/* Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


#ifndef __BL_CONFIG_H__
#define __BL_CONFIG_H__

//*****************************************************************************
//
// The following defines are used to configure the operation of the boot
// loader.  For each define, its interactions with other defines are described.
// First is the dependencies (in other words, the defines that must also be
// defined if it is defined), next are the exclusives (in other words, the
// defines that can not be defined if it is defined), and finally are the
// requirements (in other words, the defines that must be defined if it is
// defined).
//
// The following defines must be defined in order for the boot loader to
// operate:
//
//     One of CAN_ENABLE_UPDATE, SPI_ENABLE_UPDATE, SCI_ENABLE_UPDATE
//     APP_START_ADDRESS
//
//*****************************************************************************

//*****************************************************************************
//
// The frequency (MHz) of the crystal used to clock the microcontroller.
//
// This defines the crystal frequency used by the microcontroller running the
// boot loader.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define   TMS570LS31

/* 150MHz is used in this example. If you like to use different speed, please change the PLL configuration in HALCoGen*/
#define SYS_CLK_FREQ            180            //MHz, HCLK

//*****************************************************************************
// Selects the UART as the port for communicating with the boot loader.
// Exclusive of: CAN_ENABLE_UPDATE, SPI_ENABLE_UPDATE,
// Requires: UART_FIXED_BAUDRATE, BUFFER_SIZE
//*****************************************************************************
//#define UART_ENABLE_UPDATE
//#define SPI_ENABLE_UPDATE
//#define CAN_ENABLE_UPDATE

//*****************************************************************************
// The starting address of the application.  This must be a multiple of 32K(sector size)
// bytes (making it aligned to a page boundary), and can not be 0 (the first sector is
// boot loader).
//
// The flash image of the boot loader must not be larger than this value.
//*****************************************************************************
#define APP_START_ADDRESS       0x0020020

//*****************************************************************************
// The address to store the update status of the application image
// It contains Application Start Address, Application Image Size, etc
//
//*****************************************************************************
#define APP_STATUS_ADDRESS       0x0020000   /* This is must the starting address of one of flash sectors */

//*****************************************************************************
// Estimate the application image size. It is used to decide how many flash sectors
// are erased for the application image.
// The sector size is
//*****************************************************************************
#define APPLICATION_IMAGE_SIZE 0x40000;  //256KB

/* Max num bytes to be written at once. (128 bits)
 * Defined in TMS570LS3137 TRM section 5.1.2
 */
#define F021_FLASH_WRITE_WIDTH_BYTES 16

/* UART is used in all the boot modes*/
//#if defined (UART_ENABLE_UPDATE)
#define UART_BAUDRATE     115200
#define UART              scilinREG   /* Use UART port 1 for UART boot */
//#endif

#if defined (SPI_ENABLE_UPDATE)
#define SPI_PORT              spiREG2    /*use SPI2 for SPI boot*/
#endif

#if defined (CAN_ENABLE_UPDATE)
/* CAN1 is use in CAN bootloader example code. The baudrate is 500kbps, if you want to use other baudrate,
 * please configure it using HALCoGen.
 *
 * CAN Port used: DCAN1. Please configure MSG for RX, and LSG 2 for TX
 * Baudrate used: 500 kbps.
 * */
#define CAN_PORT                 canREG1
#endif

#define BUFFER_SIZE             64       /*words in the data buffer used for receiving packets*/

//*****************************************************************************
// Enables the pin-based forced update check.  When enabled, the boot loader
// will go into update mode instead of calling the application if a pin is read
// at a particular polarity, forcing an update operation.  In either case, the
// application is still able to return control to the boot loader in order to
// start an update.
//
// Requires: FORCED_UPDATE_PERIPH, FORCED_UPDATE_PORT, FORCED_UPDATE_PIN,
//           FORCED_UPDATE_POLARITY
//*****************************************************************************
#define ENABLE_UPDATE_CHECK

#if defined (ENABLE_UPDATE_CHECK)
//*****************************************************************************
//
// The GPIO port to check for a forced update.  This will be one of the
// GPIO_PORTx_BASE values, where "x" is replaced with the port name (A or B).
// Depends on: ENABLE_UPDATE_CHECK
//*****************************************************************************
#define FORCED_UPDATE_PORT      GPIO_PORTA_BASE

//*****************************************************************************
// The pin to check for a forced update.  This is a value between 0 and 7.
//
// Depends on: ENABLE_UPDATE_CHECK
//*****************************************************************************
#define FORCED_UPDATE_PIN       7

#endif

//#define   DEBUG_MSG_L3
#endif // __BL_CONFIG_H__

  • 0
    TI__Guru**** 198916 points

    Hello Greg,

    1. You can step into the APP from the dis-assembly window. 

    or

    2. comment out the instruction which checks the the APP status and GIOA[7] level. The code will jump to APP unconditionally.

        change on-chip flash option: erase necessary flash sector only

        load the APP image to x20020 , so the flash contains both BootLoader and APP, but the status field is erased to (0xFFFFFFFF).

        add breakpoint at one instruction in c_int00( of your APP    

        click CCS system reset, and start

        

  • 0 in reply to QJ Wang
    Prodigy 130 points

    I'm not entirely sure what these instructions are for?

    The code is able to jump to the beginnings of the app, but it doesn't make it to the app's main() unless I add a breakpoint to the first function call in c_init00(), and step over from there. After that, if I let it run, it will execute normally.

  • 0 in reply to Greg Baghdikian
    Prodigy 130 points

    I've discovered that if I breakpoint on line 354  and 442 in sys_startup.c and stop on both, then proceed, the App will succeed in running. Not sure what this means yet but I'm still investigating.

    I'm also unsure what the CP15 registers are showing. Here's a screenshot when the abort happens:

    /** @file sys_startup.c
    *   @brief Startup Source File
    *   @date 11-Dec-2018
    *   @version 04.07.01
    *
    *   This file contains:
    *   - Include Files
    *   - Type Definitions
    *   - External Functions
    *   - VIM RAM Setup
    *   - Startup Routine
    *   .
    *   which are relevant for the Startup.
    */

    /*
    * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
    *
    *
    *  Redistribution and use in source and binary forms, with or without
    *  modification, are permitted provided that the following conditions
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the
    *    documentation and/or other materials provided with the   
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */


    /* USER CODE BEGIN (0) */
    /* USER CODE END */


    /* Include Files */

    #include "sys_common.h"
    #include "system.h"
    #include "sys_vim.h"
    #include "sys_core.h"
    #include "sys_selftest.h"
    #include "esm.h"
    #include "mibspi.h"

    #include "errata_SSWF021_45.h"
    /* USER CODE BEGIN (1) */
    /* USER CODE END */


    /* USER CODE BEGIN (2) */
    /* USER CODE END */


    /* External Functions */
    /*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
    extern void __TI_auto_init(void);
    /*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
    extern int main(void);
    /*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
    /*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
    extern void exit(int _status);


    /* USER CODE BEGIN (3) */
    /* USER CODE END */
    void handlePLLLockFail(void);
    /* Startup Routine */
    void _c_int00(void);
    #define PLL_RETRIES 5U
    /* USER CODE BEGIN (4) */
    /* USER CODE END */

    #pragma CODE_STATE(_c_int00, 32)
    #pragma INTERRUPT(_c_int00, RESET)
    #pragma WEAK(_c_int00)

    /* SourceId : STARTUP_SourceId_001 */
    /* DesignId : STARTUP_DesignId_001 */
    /* Requirements : HL_SR508 */
    void _c_int00(void)
    {    
    /* USER CODE BEGIN (5) */
    /* USER CODE END */

        /* Initialize Core Registers to avoid CCM Error */
        _coreInitRegisters_();

    /* USER CODE BEGIN (6) */
    /* USER CODE END */

        /* Initialize Stack Pointers */
        _coreInitStackPointer_();

    /* USER CODE BEGIN (7) */
    /* USER CODE END */

        /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
         *
         * Errata Description:
         *            The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
         * Workaround:
         *            Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
        if (DEVICE_ID_REV == 0x802AAD05U)
        {
            _esmCcmErrorsClear_();
        }
        
    /* USER CODE BEGIN (8) */
    /* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();

    /* USER CODE BEGIN (11) */
    /* USER CODE END */

            /* Workaround for Errata CORTEXR4 66 */
            _errata_CORTEXR4_66_();
        
            /* Workaround for Errata CORTEXR4 57 */
            _errata_CORTEXR4_57_();

        /* Reset handler: the following instructions read from the system exception status register
         * to identify the cause of the CPU reset.
         */

        /* check for power-on reset condition */
        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
        if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
        {        
    /* USER CODE BEGIN (12) */
    /* USER CODE END */
            /* Add condition to check whether PLL can be started successfully */
            if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
            {
                /* Put system in a safe state */
                handlePLLLockFail();
            }
            /* clear all reset status flags */
            SYS_EXCEPTION = 0xFFFFU;

    /* USER CODE BEGIN (13) */
    /* USER CODE END */
    /* USER CODE BEGIN (14) */
    /* USER CODE END */
    /* USER CODE BEGIN (15) */
    /* USER CODE END */
          /* continue with normal start-up sequence */
        }
        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
        else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
        {
            /* Reset caused due to oscillator failure.
            Add user code here to handle oscillator failure */

    /* USER CODE BEGIN (16) */
    /* USER CODE END */
        }
        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
        else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
        {
            /* Reset caused due
             *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
             *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
             */
            /* Check the WatchDog Status register */
            if(WATCHDOG_STATUS != 0U)
            {
                /* Add user code here to handle watchdog violation. */
    /* USER CODE BEGIN (17) */
    /* USER CODE END */

                /* Clear the Watchdog reset flag in Exception Status register */
                SYS_EXCEPTION = WATCHDOG_RESET;
            
    /* USER CODE BEGIN (18) */
    /* USER CODE END */
            }
            else
            {
                /* Clear the ICEPICK reset flag in Exception Status register */
                SYS_EXCEPTION = ICEPICK_RESET;
    /* USER CODE BEGIN (19) */
    /* USER CODE END */
            }
        }
        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
        else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
        {
            /* Reset caused due to CPU reset.
            CPU reset can be caused by CPU self-test completion, or
            by toggling the "CPU RESET" bit of the CPU Reset Control Register. */

    /* USER CODE BEGIN (20) */
    /* USER CODE END */

            /* clear all reset status flags */
            SYS_EXCEPTION = CPU_RESET;

    /* USER CODE BEGIN (21) */
    /* USER CODE END */

        }
        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
        else if ((SYS_EXCEPTION & SW_RESET) != 0U)
        {
            /* Reset caused due to software reset.
            Add user code to handle software reset. */
            
    /* USER CODE BEGIN (22) */
    /* USER CODE END */
        }
        else
        {
            /* Reset caused by nRST being driven low externally.
            Add user code to handle external reset. */

    /* USER CODE BEGIN (23) */
    /* USER CODE END */
        }

        /* Check if there were ESM group3 errors during power-up.
         * These could occur during eFuse auto-load or during reads from flash OTP
         * during power-up. Device operation is not reliable and not recommended
         * in this case.
         * An ESM group3 error only drives the nERROR pin low. An external circuit
         * that monitors the nERROR pin must take the appropriate action to ensure that
         * the system is placed in a safe state, as determined by the application.
         */
        if ((esmREG->SR1[2]) != 0U)
        {
    /* USER CODE BEGIN (24) */
    /* USER CODE END */
        /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
        /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
            for(;;)
            {
            }/* Wait */                 
    /* USER CODE BEGIN (25) */
    /* USER CODE END */
        }

    /* USER CODE BEGIN (26) */
    /* USER CODE END */

        /* Initialize System - Clock, Flash settings with Efuse self check */
        systemInit();
        
        /* Workaround for Errata PBIST#4 */
        errata_PBIST_4();
        
        /* Run a diagnostic check on the memory self-test controller.
         * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
         * The memory self-test is expected to fail. The function ensures that the PBIST controller
         * is capable of detecting and indicating a memory self-test failure.
         */
        pbistSelfCheck();    
        
        /* Run PBIST on STC ROM */
        pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
                 ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
        
        /* Wait for PBIST for STC ROM to be completed */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while(pbistIsTestCompleted() != TRUE)
        {
        }/* Wait */
        
        /* Check if PBIST on STC ROM passed the self-test */
        if( pbistIsTestPassed() != TRUE)
        {
            /* PBIST and STC ROM failed the self-test.
             * Need custom handler to check the memory failure
             * and to take the appropriate next step.
             */
             
            pbistFail();

        }   
        
        /* Disable PBIST clocks and disable memory self-test mode */
        pbistStop();

        /* Run PBIST on PBIST ROM */
        pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
                 ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
        
        /* Wait for PBIST for PBIST ROM to be completed */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while(pbistIsTestCompleted() != TRUE)
        {
        }/* Wait */
        
        /* Check if PBIST ROM passed the self-test */
        if( pbistIsTestPassed() != TRUE)
        {
            /* PBIST and STC ROM failed the self-test.
             * Need custom handler to check the memory failure
             * and to take the appropriate next step.
             */
             
            pbistFail();

        }
        
        /* Disable PBIST clocks and disable memory self-test mode */
        pbistStop();    
    /* USER CODE BEGIN (29) */
    /* USER CODE END */

    /* USER CODE BEGIN (31) */
    /* USER CODE END */

        /* Disable RAM ECC before doing PBIST for Main RAM */
        _coreDisableRamEcc_();
        
        /* Run PBIST on CPU RAM.
         * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
         * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
         * device datasheet.
         */
        pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
                 (uint32)PBIST_March13N_SP);

    /* USER CODE BEGIN (32) */
    /* USER CODE END */

        /* Wait for PBIST for CPU RAM to be completed */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while(pbistIsTestCompleted() != TRUE)
        {
        }/* Wait */                 
        

    /* USER CODE BEGIN (33) */
    /* USER CODE END */
        
        /* Check if CPU RAM passed the self-test */
        if( pbistIsTestPassed() != TRUE)
        {
            /* CPU RAM failed the self-test.
             * Need custom handler to check the memory failure
             * and to take the appropriate next step.
             */
    /* USER CODE BEGIN (34) */
    /* USER CODE END */
             
            pbistFail();
            
    /* USER CODE BEGIN (35) */
    /* USER CODE END */
        }

    /* USER CODE BEGIN (36) */
    /* USER CODE END */

        /* Disable PBIST clocks and disable memory self-test mode */
        pbistStop();

        
    /* USER CODE BEGIN (37) */
    /* USER CODE END */


        /* Initialize CPU RAM.
         * This function uses the system module's hardware for auto-initialization of memories and their
         * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
         * Hence the value 0x1 passed to the function.
         * This function will initialize the entire CPU RAM and the corresponding ECC locations.
         */
        memoryInit(0x1U);

    /* USER CODE BEGIN (38) */
    /* USER CODE END */
        
        /* Enable ECC checking for TCRAM accesses.
         * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
         */
        _coreEnableRamEcc_();

    /* USER CODE BEGIN (39) */
    /* USER CODE END */

        /* Start PBIST on all dual-port memories */
        /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
           PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
         */
        pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
                 | (uint32)0x00000000U    /* USB RAM */  
                 | (uint32)0x00000800U    /* DMA RAM */
                 | (uint32)0x00000200U    /* VIM RAM */
                 | (uint32)0x00000040U    /* MIBSPI1 RAM */
                 | (uint32)0x00000080U    /* MIBSPI3 RAM */
                 | (uint32)0x00000100U    /* MIBSPI5 RAM */
                 | (uint32)0x00000004U    /* CAN1 RAM */
                 | (uint32)0x00000008U    /* CAN2 RAM */
                 | (uint32)0x00000010U    /* CAN3 RAM */
                 | (uint32)0x00000400U    /* ADC1 RAM */
                 | (uint32)0x00020000U    /* ADC2 RAM */
                 | (uint32)0x00001000U    /* HET1 RAM */
                 | (uint32)0x00040000U    /* HET2 RAM */
                 | (uint32)0x00002000U    /* HTU1 RAM */
                 | (uint32)0x00080000U    /* HTU2 RAM */
                 | (uint32)0x00004000U    /* RTP RAM */
                 | (uint32)0x00008000U    /* FRAY RAM */
                 ,(uint32) PBIST_March13N_DP);

    /* USER CODE BEGIN (40) */
    /* USER CODE END */

        /* Test the CPU ECC mechanism for RAM accesses.
         * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
         * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
         * in the ECC causes a data abort exception. The data abort handler is written to look for
         * deliberately caused exception and to return the code execution to the instruction
         * following the one that caused the abort.
         */
        checkRAMECC();

    /* USER CODE BEGIN (41) */
    /* USER CODE END */
    /* USER CODE BEGIN (43) */
    /* USER CODE END */

        /* Wait for PBIST for CPU RAM to be completed */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while(pbistIsTestCompleted() != TRUE)
        {
        }/* Wait */                 
        

    /* USER CODE BEGIN (44) */
    /* USER CODE END */

        /* Check if CPU RAM passed the self-test */
        if( pbistIsTestPassed() != TRUE)
        {

    /* USER CODE BEGIN (45) */
    /* USER CODE END */

            /* CPU RAM failed the self-test.
             * Need custom handler to check the memory failure
             * and to take the appropriate next step.
             */
    /* USER CODE BEGIN (46) */
    /* USER CODE END */
             
            pbistFail();
            
    /* USER CODE BEGIN (47) */
    /* USER CODE END */
        }

    /* USER CODE BEGIN (48) */
    /* USER CODE END */

        /* Disable PBIST clocks and disable memory self-test mode */
        pbistStop();
        
    /* USER CODE BEGIN (55) */
    /* USER CODE END */

        /* Release the MibSPI1 modules from local reset.
         * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
         */
         mibspiREG1->GCR0 = 0x1U;
         
        /* Release the MibSPI3 modules from local reset.
         * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
         */
        mibspiREG3->GCR0 = 0x1U;
        
        /* Release the MibSPI5 modules from local reset.
         * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
         */
        mibspiREG5->GCR0 = 0x1U;
        
    /* USER CODE BEGIN (56) */
    /* USER CODE END */

        /* Enable parity on selected RAMs */
        enableParity();
        
        /* Initialize all on-chip SRAMs except for MibSPIx RAMs
         * The MibSPIx modules have their own auto-initialization mechanism which is triggered
         * as soon as the modules are brought out of local reset.
         */
        /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
         */
        /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
                  Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
         */
        memoryInit( (uint32)((uint32)1U << 1U)    /* DMA RAM */
                  | (uint32)((uint32)1U << 2U)    /* VIM RAM */
                  | (uint32)((uint32)1U << 5U)    /* CAN1 RAM */
                  | (uint32)((uint32)1U << 6U)    /* CAN2 RAM */
                  | (uint32)((uint32)1U << 10U)   /* CAN3 RAM */
                  | (uint32)((uint32)1U << 8U)    /* ADC1 RAM */
                  | (uint32)((uint32)1U << 14U)   /* ADC2 RAM */
                  | (uint32)((uint32)1U << 3U)    /* HET1 RAM */
                  | (uint32)((uint32)1U << 4U)    /* HTU1 RAM */
                  | (uint32)((uint32)1U << 15U)   /* HET2 RAM */
                  | (uint32)((uint32)1U << 16U)   /* HTU2 RAM */
                  );

        /* Disable parity */
        disableParity();
        
        /* Test the parity protection mechanism for peripheral RAMs
           NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
                     Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
        */

    /* USER CODE BEGIN (57) */
    /* USER CODE END */
         
        het1ParityCheck();
        
    /* USER CODE BEGIN (58) */
    /* USER CODE END */

        htu1ParityCheck();
        
    /* USER CODE BEGIN (59) */
    /* USER CODE END */

        het2ParityCheck();
        
    /* USER CODE BEGIN (60) */
    /* USER CODE END */

        htu2ParityCheck();
        
    /* USER CODE BEGIN (61) */
    /* USER CODE END */

        adc1ParityCheck();
        
    /* USER CODE BEGIN (62) */
    /* USER CODE END */

        adc2ParityCheck();
        
    /* USER CODE BEGIN (63) */
    /* USER CODE END */

        can1ParityCheck();
        
    /* USER CODE BEGIN (64) */
    /* USER CODE END */

        can2ParityCheck();
        
    /* USER CODE BEGIN (65) */
    /* USER CODE END */

        can3ParityCheck();
        
    /* USER CODE BEGIN (66) */
    /* USER CODE END */

        vimParityCheck();
        
    /* USER CODE BEGIN (67) */
    /* USER CODE END */

        dmaParityCheck();


    /* USER CODE BEGIN (68) */
    /* USER CODE END */

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
        {
        }/* Wait */                 
        /* wait for MibSPI1 RAM to complete initialization */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
        {
        }/* Wait */                 
        /* wait for MibSPI3 RAM to complete initialization */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
        {
        }/* Wait */                 
        /* wait for MibSPI5 RAM to complete initialization */

    /* USER CODE BEGIN (69) */
    /* USER CODE END */

        mibspi1ParityCheck();
        
    /* USER CODE BEGIN (70) */
    /* USER CODE END */

        mibspi3ParityCheck();
        
    /* USER CODE BEGIN (71) */
    /* USER CODE END */
        
        mibspi5ParityCheck();
        

    /* USER CODE BEGIN (72) */
    /* USER CODE END */
        
        /* Enable IRQ offset via Vic controller */
        _coreEnableIrqVicOffset_();
        

    /* USER CODE BEGIN (73) */
    /* USER CODE END */

        /* Initialize VIM table */
        vimInit();    

    /* USER CODE BEGIN (74) */
    /* USER CODE END */

        /* Configure system response to error conditions signaled to the ESM group1 */
        /* This function can be configured from the ESM tab of HALCoGen */
        esmInit();
        /* initialize copy table */
        __TI_auto_init();
    /* USER CODE BEGIN (75) */
    /* USER CODE END */
        
        /* call the application */
    /*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
    /*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
    /*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
        main();

    /* USER CODE BEGIN (76) */
    /* USER CODE END */
    /*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
        exit(0);

    /* USER CODE BEGIN (77) */
    /* USER CODE END */
    }

    /* USER CODE BEGIN (78) */
    /* USER CODE END */
    /** @fn void handlePLLLockFail(void)
    *   @brief This function handles PLL lock fail.
    */
    void handlePLLLockFail(void)
    {
    /* USER CODE BEGIN (79) */
    /* USER CODE END */
        while(1)
        {
            
        }
    /* USER CODE BEGIN (80) */
    /* USER CODE END */
    }
    /* USER CODE BEGIN (81) */
    /* USER CODE END */

  • 0 in reply to Greg Baghdikian
    TI__Guru**** 198916 points

    Have you resolved the problem?

  • 0 in reply to QJ Wang
    Prodigy 130 points

    I have, I used the UART bootloader example and modified it to use with the TFTP example.

  • 0 in reply to Greg Baghdikian
    TI__Guru**** 198916 points

    Nice to know it. Thanks