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Reset states of R4F Core E and T flags

Chris Abbott54224
Prodigy 120 points

Hi, i have been trying to find this in the documentation but nothing is directly specified.

The ARM specification (DDI0363R_cortexr4_r1p3_trm.pdf) for the Cortex-R4 core (which is never referenced by any TI document) states that upon a Reset:

  1. CPU E Flag (endianness) is determined by the state of the CFGEE pin
  2. CPU T Flag (ARM/Thumb) is determined by the state of the TEINIT pin

a) These pins (core configuration signals) are not mentioned at all

b) Endianness is specified in the TI manual (section 1.4), as being fixed in the "big endian BE-32" mode, which is contrary to the ARM cortex-R4 model (section 2.10)

c) We are getting problems when a debugger is connected that the T flag is in-determinate at power on, which leads us to believe this is being read from a real IO pin that is probably not pulled up/down as required.

  • 0
    TI__Intellectual 2285 points

    Your question has been routed to relevant expert.

    For additional clarification , which Micro and which debugger/sw tool chain are you using ?

    Regards,

    Pratip

     

  • 0 in reply to Pratip Kumar
    Prodigy 120 points

    Additional Info:

     

    CPU = TMS570LS20216ASZWTQQI

    Debug = Lauterbach Power Debug with ARM-A/R cable (latest version)

    SW = IAR Embedded Workbench - ARM (latest version)

  • 0
    TI__Expert 7650 points

    Hi Chris,

    The pins referenced by the ARM documentation refer to straps on the Cortex-R4 core IP itself.  In the TMS570 implementation of these cores, CFGEE and TEINIT are managed by our hardware design.  The TI documents correctly state that the core is fixed in BE32 mode.  Since the ARM documents are more generic (more Endianism options available) this can come across confusing.  However, for your use, please know that the TMS570 family is a BE32 family. 

    Regarding c), the T flag, I will have to look into this but I am not aware of any external IO pin read to determine ARM vs. Thumb.

  • 0
    TI__Mastermind 23000 points

    Hi Chris,

    The TMS570LS series TRM (SPRU489A) contains references to the R4F TRM version r1p3 from ARM (p. 50, p. 245).  The R4F is configurable and can be implemented in many different ways.  The CFGEE, TEINIT, and several dozen other configuration options sampled at boot time are fixed in silicon.  There is no IO pin configurability for the CPU implementation options.

    Endianness is fixed at system level to BE-32.  The CPU will report BE-8 endianness, as it does not natively support BE-32.  TI made this design decision in order to enable compatibility with our earlier TMS470R1x and TMS470Pxx product lines which utilize ARM7TDMI.  The endianness support is described on pg. 21 of the TRM.

    At reset, the core will boot in ARM state.  This is also to enable backwards compatibility with the previous TMS470R1x and TMS470Pxx product lines which utilize ARM7TDMI.  This is not clearly stated in the TRM and I will submit a ticket to improve the documentation.

    I am a bit puzzled as to why you do not see the flags clearly with your tool set.  I suspect this is a tool issue, as I have not seen this problem with the TI tool suite.

    Best Regards,

    Karl