How to set ASEL for BCDMA/PKTDMA.

Boshra

Other Parts Discussed in Thread: AM6442

I am using the board AM6442 HS-FS device, and my question is regarding the ASEL setting for BCDMA/PKTDMA.

Despite in the latest TRM of AM64x a section related to ASEL is added, it is still not clear to me. I have the following questions:

What is the usage of ASEL, and how it should be defined for BCDMA/PKTDMA
What does it mean when I set the ASEL= 0?
I believe DMASS (pktdma/bcdma) is not using the MPU and it's only for the accesses that are related to the CPU, so what does it mean to have a cache allocation for them in the MPU?

Thanks,

Boshra

over 2 years ago

0 Dominic Rath over 2 years ago

Mastermind 7730 points

You can set ASEL to make DMA accesses coherent with the A53. These acceses can optionally allocate into A53 caches, e.g. to pre-warm caches with data the A53 is going to access soon after.

It should also be possible to have DMA directly access PCIe space, but I guess that's a more exotic use case.

Please note I'm not TI, they might have other answers for you.

Regards, Dominic

0 Boshra over 2 years ago in reply to Dominic Rath

Intellectual 418 points

Im not even using A53, how about R5? Im only using one core actually, R5f_0_0

0 Dominic Rath over 2 years ago in reply to Boshra

Mastermind 7730 points

Hmm, not sure if ASEL would really have any effect for you.

The R5f on the AM64x doesn't support coherency.

+1 Pekka Varis over 2 years ago in reply to Dominic Rath

TI__Mastermind 27050 points

ASEL is only relevant for A53 cache coherency in AM64x and then for PCIe to bypass address translations and use entire 64-bit address instead of just the window in the global memory map. See section "3.5 IO Coherency Support" in the TRM, and then the QOS registers description (such as "3.10.1.1175 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_MAP0 Registers").

ASEL = 0 is default, and based on your description above you don't need to touch it.

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How to set ASEL for BCDMA/PKTDMA.