Hi Pengfei,

Thank you for the information.

But, when I tried to flash the firmware after building with Linker File Generation, Startup File Reference disabled (in order to editing device_linker.cmd) i am getting errors:

CORTEX_M0P: Flash Programmer: Error in image size. Length of block is 246, but it should be divisible by 8 since Flash Programmer writes in 64-bits

Thank you

Hi 

I assume you are using Uniflash for programming.

Please follow the instruction of below for setting output file format.

(+) MSPM0G1519: Uniflash error with MSPM0G1519 - Arm-based microcontrollers - INTERNAL forum - Arm-based microcontrollers - INTERNAL - TI E2E support forums

Hi,

I'm getting that error in both CCS and Uniflash. The link is not working

Hi

Thanks for support. I'll try to look into the jumping code later.

But, now I have a urgent issue to solve. From the secondary bootloader, I am able to receive firmware bytes (34kb) over CAN and write it at 0x12800 location and able to calculate CRC successfully. But, when trying to copy the code from 0x12800 to 0x0, I'm facing error (gErrorType = ERROR_64BIT_W) when writing at 0x1000. Below is the code I'm using to write at 0x0 as well as 0x12800. Can you please support on this process.

uint8_t nvm_write(uint32_t write_address, uint32_t *fw_word)
{

    if (gErrorType == NO_ERROR) {
            /*
            * 64-bit write to flash in main memory with ECC generated by hardware.
            * Data must be loaded 32-bits at a time, but a single word program
            * is executed
            */
            DL_CORE_configInstruction(CPUSS_CTL_ICACHE_DISABLE,
            CPUSS_CTL_PREFETCH_DISABLE, CPUSS_CTL_LITEN_DISABLE);                       //Disabling cache
            

             //flash word writer
             DL_FlashCTL_unprotectSector(
                     FLASHCTL, write_address, DL_FLASHCTL_REGION_SELECT_MAIN);
             gCmdStatus = DL_FlashCTL_programMemoryFromRAM64WithECCGenerated(
                     FLASHCTL, write_address, &fw_word[0]);

             DL_CORE_configInstruction(CPUSS_CTL_ICACHE_ENABLE,
                 CPUSS_CTL_PREFETCH_ENABLE, CPUSS_CTL_LITEN_ENABLE);                    //Enabling cache

             if (gCmdStatus == DL_FLASHCTL_COMMAND_STATUS_FAILED) {
                     /* If command was not successful, set error flag */
                     gErrorType = ERROR_64BIT_W;
                 }
    }
    return gErrorType;
}

Hi，

If you are using the secondary_bsl example in our SDK and did not make any change, please notice that this secondary_bsl program is placed at the address of 0x1000. (0x1000 for interrupt vector table, 0x1040 for program). So it is not allowed to erase and problem this region with program running. 

If you still want to program your image at 0x00 address, please define a larger start address in .cmd file and also redefine the Alternate BSL Address in sysconfig (it value should be FLASH_SBSL_START address + 1)

Hi,

I have updated the .cmd file. Also I have updated in sysconfig as FLASH_SBSL_START address + 1 earlier itself. Still doesn't work.
 

-uinterruptVectors
--stack_size=512
/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
//    FLASH_SBSL_INTVEC(RWX)  :	 org = 0x00001000,      len = 0x00000040,
//    FLASH_SBSL_START(RWX)   :	 org = 0x00001040,      len = 0x00000040,
//    FLASH_SBSL(RWX)   	    :	 org = 0x00001080,      len = 0x00003400,
    FLASH_SBSL_INTVEC(RWX)  :	 org = 0x000D800,      len = 0x00000040,
    FLASH_SBSL_START(RWX)   :	 org = 0x000D840,      len = 0x00000040,
    FLASH_SBSL(RWX)   		:	 org = 0x000D880,      len = 0x00003400,

    SRAM(RW)				:    org = 0x20000000,      len = 0x00008000,

    BCR_CFG		 		    : 	 org = 0x41C00000,      len = 0x00000080,
    BSL_CFG				    : 	 org = 0x41C00100,      len = 0x00000080,
    FACTORY_CFG		  		: 	 org = 0x41C40000,      len = 0x00000200,
}

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
	.intvecs			: PALIGN(8) {} > FLASH_SBSL_INTVEC
	.sblStart			: PALIGN(8) {} > FLASH_SBSL_START

    GROUP(FLASH_MEMORY) {
        .text          	: PALIGN(8) {}
        .const         	: PALIGN(8) {}
        .cinit         	: PALIGN(8) {}
        .rodata			: PALIGN(8) {}
    } > FLASH_SBSL

    GROUP(SRAM) {
        .vtable 		: {}
        .data          	: {}
        .bss           	: {}
   } > SRAM

    .stack  :   > SRAM (HIGH) SIZE(BSL_CI_stackSize)
    .binit        : palign(8) {} > FLASH_SBSL
    .TI.ramfunc   : load = FLASH_SBSL, palign(8), run=SRAM, table(BINIT)

    .factoryConfig          : {} > FACTORY_CFG
    .BCRConfig              : {} > BCR_CFG
    .BSLConfig              : {} > BSL_CFG
}

Hi,

Sorry I miss an item to modify: Change the static write protection of MAIN low sectors. Below is the static write protection for default 0x1000-0x8000. One bit is for a sector, you need to change it to the protected region of your secondary BSL program.

Please refer 4.3.1 Flash-Based Secondary BSL Start From 0x1000 of MSPM0 Bootloader (BSL) Implementation (Rev. C)

As for the flash write example in SDK, the error is because in this example, only the sector of MAIN_BASE_ADDRESS is unprotected, so if it is set as 0xFF8, the next sector (0x1000) is protected, and not allowed to be programmed. 

Hi,

Thank you for the information.

Corresponding to the jumping of Stack Pointer, I have updated the .cmd linker file correspondingly and now I am able to jump the SP to 0x5800 where the main App is and successfully execute the app. I am storing the secondary bootloader at 0x1000. This process is working fine. I'll proceed with the same.

Thank you for helping me solve this issue.

Regards,
Vineeth