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TDA4VEN-Q1: TDA4 single-link mode, no signal on OLDI clock pins.

HC Nong
Prodigy 100 points

Part Number: TDA4VEN-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi expert,
    

TDA4VEN runs the video streaming pipeline on the MAIN R5F and outputs it to the display via the OLDI0 interface. The timing diagram I used is shown below, operating in Single Link mode with Dual Mode Sync disabled. The entire graph runs without any errors, but there is no clock signal waveform on the OLDI0_CLK0P and OLDI0_CLK0N pins of the SoC, resulting in no data being displayed on the screen.

When using the dual link mode of the DSS, there is no issue—the screen can light up and display data normally. However, since only four lanes are connected, half of the data is lost. Therefore, I need to switch to single link mode, which led to the problem described above.

My pixel clock calculation is as follows:
(1920 + 36 + 36 + 36) × (1080 + 8 + 32 + 2) × 60 × 7 = 955,674,720

Could you please help me understand why there is no output waveform on the OLDI0 clock signal lines in single link mode?

ba4c0c99-a081-4745-8b3f-b82bd38856f4.png

Best wishes.

  • 0
    Prodigy 100 points

    And how to solve this problem?

  • 0 in reply to HC Nong
    TI__Guru**** 504305 points

    Hi Nong,

    Sorry, "The entire graph runs without any errors,", can you elaborate on this? Are you trying to enable OLDI output in OpenVX graph? OpenVX currently does not support OLDI output. 

    Also can you pls check in the code if it is setting the pixel clock correctly? Sometime the clock could be fixed in the example code.. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 100 points

    Hi ,

            As I mentioned earlier, in the OLDI dual link mode, the screen can display images normally. However, in the OLDI single link mode, the screen fails to show any picture, and there is no clock signal on the OLDI clock pin, although there is data signal on the data pins. I can confirm that the screen timing is correct, so this should not be an issue of OpenVX not supporting OLDI output. Instead, it seems to be a problem with the SoC's OLDI interface failing to output the clock signal in single link mode.

            As for "The entire graph runs without any errors," graph, its output log is exactly the same as the log when the screen can display the image normally, and we have no idea what to do.

      

    Regards,

    Nong

  • 0 in reply to HC Nong
    TI__Guru**** 504305 points

    Hi Nong,

    I checked with the team internally and confirmed that single link mode is not validated in the SDK.. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 100 points

    Hi Brijesh ,

        Given the demands of our team's current development projects, we have no choice but to adopt the single-link transmission mode. Could you please coordinate the necessary resources to implement the OLDI video output supporting single-link mode in the SDK?

    Regards,

    Brijesh

  • 0 in reply to HC Nong
    TI__Guru**** 504305 points

    Hi Nong,

    Can you please raise it to your local field support? 

    Also there is a limitation on EVM, we dont have a way to validate single link output mode.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Expert 4245 points

     Can you please confirm the calculation to PCLK in sysconfig is correct?

    (1920 + 36 + 36 + 36) × (1080 + 8 + 32 + 2) × 60 × 7 = 955,674,720? Is there is difference b/w single link v.s. dual link, for example to x14 instead of x7??