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Regarding Flash ECC in TMS570 serise

Hello,

I is using TMS570 for security PLC application and is looking for some documentations on Flash ECC.

There is no explanation for FDIAGCTRL, FPAROVR registers in TRM (SPNU489C). Please let know if there is any updated TRM which documents FDIAGCTRL, FPAROVR registers. Also, does flashBadECC address (0x20080000) apply to all TMS570 series? Or do TMS570 series have different addresses for flashbadECC?

Thank you.

  • These two registers do not exist on TMS570LS2x2x.

    You can find following code in the TMS570LS2x demo software, which create a Flash ECC fault.

    void ATCM_Correctable_Error(void)

    {

    unsigned int Single_Bit_Err_Loc;

    /** - 0x604204 is TI OTP location which has corrupted data "0x9ABCDEF1" */

    unsigned int * Single_Bit_Err_Loc_ptr = (unsigned int *)(0x0604204);

    /** - Setup Flash ECC* - Error Detection / Correction Enable

    * - Erros from OTP memory regions unblocked

    * - Correctable Interrupt Enabled

    */

    FLASHW->FEDACCTRL1 = 0x20D;

    /** Enable Flash ECC in Cortex R4*/

    _coreEnableFlashEcc_();

    /** - Read data from the Single Bit Error location

    * - ESM error will be triggered after this read

    * - Data will be corrected and stored in the variable Single_Bit_Err_Loc

    */

    Single_Bit_Err_Loc = * Single_Bit_Err_Loc_ptr;

    /** - Verify that corrected data is stored in the variable

    * - Transmit back 0x0000000 to PC incase of failure

    */

    if (Single_Bit_Err_Loc != 0x9ABCDEF0)

    {

    sciSend_32bitdata(sciREG1, FAIL);

    }

    /** - Clear the Flash Single Bit error Flag */

    FLASHW->FEDACSTATUS = 2;

    /** - Disable Flash Error Detection / Correction */

    FLASHW->FEDACCTRL1 = 0x005;

    /** Disable Flash ECC in Cortex R4*/

    _coreDisableFlashEcc_();

    }

  • Thomas,

    What is the status of your post? Did we answered your question? If yes, can you please mark our answer as "Verified Answer" so we can close this thread.